An active device and circuits utilized therewith are disclosed. In an aspect, the active device comprises an n-type transistor having a drain, gate and bulk and a p-type transistor having a drain, gate and bulk. The n-type transistor and the p-type transistor include a common source. The device includes a first capacitor coupled between the gate of the n-type transistor and the gate of the p-type transistor, a second capacitor coupled between the drain of the n-type transistor and the drain of p-type transistor and a third capacitor coupled between the bulk of the n-type transistor and the bulk of p-type transistor. The active device has a high breakdown voltage, is memory less and traps even harmonic signals.

Metal pillars are placed adjacent to transistor arrays in the power amplifiers that can be used in wireless devices. By placing the metal pillars in intimate contact with the silicon substrate and not over a substantial portion of the transistor arrays, the heat generated by the transistor arrays flows down into the silicon substrate and out the metal pillar. The metal pillar forms a solder bump of a flip chip power amplifier die, which when soldered to a module, further conducts the heat away from the transistor array.

Embodiments of the disclosure generally relate to a method and device for improving the efficiency of a power amplifier. The apparatus comprising: a harmonic generator, configured to generate one or more harmonic according to an output signal of a power amplifier; a harmonic feedback device, configured to inject the harmonic generated by the harmonic generator to an input terminal of the power amplifier; and a harmonic eliminator, configured to eliminate the harmonic in the output signal of the power amplifier. According to embodiments of the disclosure, the efficiency of power amplifier can be improved without degrading the linearity.

A current compensation circuit for providing a current to an amplifier circuit includes a first amplifier, a first transistor and a first bias circuit. The first bias circuit provides a first bias current to the first amplifier. The current compensation circuit includes a power detection circuit, an operational amplifier circuit and a current-to-voltage converter. The power detection circuit detects and converts an input power or an output power of the first amplifier to a first detection voltage. The operational amplifier circuit generates a second detection voltage according to the first detection voltage and a calibration voltage. The current-to-voltage converter converts the second detection voltage to a compensation current. A first compensation current flows to the first amplifier through the first transistor according to the compensation current, such that the first amplifier is driven by the first bias current plus the first compensation current.

A calibration system of architecture, apparatus, algorithms and method for optimizing leakage performance of a multi-port amplifier (MPA) for satellite communications. The calibration system comprises simple onboard apparatus and generally on-ground algorithms implementation connected via telecommand and telemetry links. The isolation performance of the MPA is monitored by using a commandable frequency generator and a flexible narrowband receiver. The high performance is achieved by direct and efficient optimization of the aggregate leakage of the MPA. The calibration system may be applied but not limited to Ku and Ka-band high throughput satellite systems.

Embodiments of linear equalizers are disclosed. In an embodiment, a linear equalizer includes sets of transistors, a resistor, and first and second impedance elements. The sets of transistors are connected between at least one input terminal of the linear equalizer and at least one output terminal of the linear equalizer. The resistor is connected to a supply voltage, to the at least one output terminal, and to the sets of transistors. The first and second impedance elements are connected between emitter terminals or source terminals of the sets of transistors and at least one fixed voltage. A peaking gain of the linear equalizer is programmable by adjusting a direct current (DC) component of at least one input signal that is received at the at least one input terminal and that is applied to the sets of transistors.

A power combiner for an outphasing amplifier system comprises an output terminal, a first input terminal, a first inductor, and a first capacitor, wherein the first input terminal is connected to ground via the first inductor and the first input terminal is connected to the output terminal via the first capacitor. The power combiner further comprises a second input terminal, a second capacitor, and a second inductor, wherein the second input terminal is connected to ground via the second capacitor and the second input terminal is connected to the output terminal via the second inductor. The first capacitor can have a same capacitance as the second capacitor and the first inductor has a same inductance as the second inductor.

A MMIC support and cooling structure having a three-dimensional, thermally conductive support structure having a plurality of surfaces and a circuit having a plurality of heat generating electrical components disposed on a first portion of the surfaces and interconnected by microwave transmission lines disposed on a second portion of the plurality of surfaces of the thermally conductive support structure

A power amplifier circuit is capable of restraining uneven temperature distribution among a plurality of unit transistors while restraining the deterioration of the characteristics of the power amplifier circuit. The power amplifier circuit includes: a first transistor group which includes a plurality of unit transistors and which amplifies an input signal and outputs an amplified signal; a bias circuit which supplies a bias current or a bias voltage to a base or a gate of each unit transistor of the first transistor group; a plurality of first resistive elements, each of which is connected between the base or the gate of each unit transistor of the first transistor group and an output of the bias circuit; and a plurality of second resistive elements, each of which is connected between an emitter or a source of each unit transistor of the first transistor group and a reference potential.

A power amplifier circuit includes a differential to single-ended converter, a gain stage circuit, a driver stage circuit, and an output stage circuit connected in series, and a bias circuit connected to a bias voltage port of the gain stage circuit for adjusting a bias voltage of the gain stage circuit. The bias voltage is adjustable to ensure low power consumption, improve the efficiency of the power amplifier circuit and prevent process, voltage and temperatures from affecting the performance of the power amplifier circuit.