A power amplifier includes a two-dimensional matrix of NM active cells formed by stacking main terminals of multiple active cells in series. The stacks are coupled in parallel to form the two-dimensional matrix. The power amplifier includes a driver structure to coordinate the driving of the active cells so that the effective output power of the two-dimensional matrix is approximately NM the output power of each of the active cells.

A power amplifier includes an amplifying circuit configured to amplify an input signal and comprising transistors, which may be disposed in parallel with one another and divided into a first group of transistors and a second group of transistors. The power amplifier also includes a bias circuit configured to supply bias power to one of the transistors of the first group and the transistors of the second group.

An amplification circuit includes: a current source; a first input transistor pair suitable for receiving a positive input voltage and having a split-length gate structure; a second input transistor pair suitable for receiving a negative input voltage and having a split-length gate structure; an enable unit suitable for supplying a current from the current source to each of the first input transistor pair and the second input transistor pair in response to an enable signal; a switching unit suitable for coupling a second split gate node between the second input transistor pair to a compensation capacitor node during an activation section of the enable signal; and a compensation driving unit suitable for compensating and driving a first split gate node between the first input transistor pair at an initial stage of the activation section of the enable signal.

Power amplifiers having reduced loss. In some embodiments, a power amplification system can include a plurality of power amplifiers, with each power amplifier being configured to receive and amplify a signal in a frequency band. The power amplification system can further include an output filter coupled to each of the power amplifiers by a separate output path such that the power amplification system is substantially free of a band selection switch between the plurality of power amplifiers and their corresponding output filters. Each power amplifier can be further configured to operate with a high-voltage supply to provide an impedance similar to an impedance of the corresponding output filter.

The present disclosure provides a gradient amplifier driver stage circuit, a gradient amplifier system and a control method thereof. The gradient amplifier driver stage circuit includes: a gradient coil and a plurality of gradient driver modules electrically cascaded with each other and forming an output end, the output end being electrically connected to the gradient coil, wherein each gradient driver module includes a pre-stage power supply and a bridge amplifier connected in parallel, output voltage of the pre-stage power supplies of the plurality of gradient driver modules are the same, and each gradient driver module is configured to provide an inductive voltage drop and a resistive voltage drop on the gradient coil.

An improved method of providing high burst power to audio amplifiers from limited power sources, using parallel power paths to increase system efficiency without need for a power path controller, thus utilizing a simplified circuit operation and maximizing average power available for both the amplifier and supporting circuitry.

An active device and circuits utilized therewith are disclosed. In an aspect, the active device comprises an n-type transistor having a drain, gate and bulk and a p-type transistor having a drain, gate and bulk. The n-type transistor and the p-type transistor include a common source. The device includes a first capacitor coupled between the gate of the n-type transistor and the gale of the p-type transistor, a second capacitor coupled between the drain of the n-type transistor and the drain of p-type transistor and a third capacitor coupled between the bulk of the n-type transistor and the bulk of p-type transistor. The active device has a high breakdown voltage, is memory less and traps even harmonic signals.

A resistor array made of a semiconductor includes a plurality of resistor groups and a common line that electrically connects the M-th resistors of the plurality of resistor groups. Each resistor group includes first to M-th resistors connected in series, M being an integer of 2 or greater, and at least one short-circuit line, each short-circuiting at least one, but not all, of the M resistors.

A detector circuit includes a first inverter including an input node coupled via a first capacitor to a transmission path for transmitting an AC signal, the first inverter outputting an output voltage in accordance with power of the AC signal, wherein the output voltage increases with increasing temperature, a second inverter including an input node coupled to the transmission path, the second inverter outputting an output voltage in accordance with power of the AC signal, wherein the output voltage decreases with increasing temperature, a third capacitor including one electrode coupled to either an output electrode of the first inverter or an output node of the second inverter, a first resistor coupled between the output node of the first inverter and an output node of the detector circuit, and a second resistor coupled between the output node of the second inverter and the output node of the detector circuit.

A protection circuit for use in an RF active circuit includes a signal strength detecting circuit, a current detecting circuit, a logic circuit, and a switching unit. The signal strength detecting circuit is coupled to the signal input end or the signal output end of the RF active circuit and configured to generate a first detecting signal according to the signal strength of the RF signal. The current detecting circuit is configured to detect the VSWR of the RF signal based on the driving current of the RF active circuit, thereby generating a corresponding second detecting signal. The logic circuit is configured to generate a switch control signal according to the first detecting signal and the second detecting signal. The switching unit is configured to lower the driving current of the RF active circuit according to the switch control signal.