Various aspects of integrated amplifiers, layouts for the integrated amplifiers, and packaged arrangements of the amplifiers are described. In one example, an amplifier includes an amplifier cell, and a biasing network coupled to the common gate transistor in the amplifier cell. The amplifier cell includes a common source transistor and a common gate transistor in a cascode arrangement, where at least one of the common source transistor and the common gate transistor comprises a field plate. Among other advantages, the amplifiers described herein can be biased with relatively high voltages and still operate like a single a common source transistor, without sacrificing reliability, performance, or requiring additional off-chip components, such as biasing networks of resistors and inductors.

A power amplifier arrangement (200) for amplifying an input signal to produce an output signal comprises a plurality N of amplifier sections (212, 213), a first input transmission line (221) comprising multiple segments and a first output transmission line (231) comprising multiple segments. Each amplifier section comprises one or more first transistors (T1) distributed along the first input transmission line (221) and the first output transmission line (231). Each amplifier section is configured to amplify a portion of the input signal to produce a portion of the output signal. A portion of the input signal is one of N portions of the input signal partitioned on any one or a combination of an amplitude basis and a time basis. The output signal is produced at an end of the first output transmission line (231) by building up N potions of the output signal from each amplifier section.

A dual amplifier apparatus is disclosed. The apparatus includes an energy module having a controller and a first and second power amplifier circuit coupled to the controller. The first and second power amplifier circuits are configured to receive and amplify an input signal to generate a first output signal into a load coupled to the output of the first and second power amplifier circuit. A power rating of the first amplifier circuit is different from a power rating of the second amplifier circuit. The controller is configured to select the first or the second power amplifier circuit.

Methods and apparatus for implementing a power efficient amplifier device through the use of a main (primary) and auxiliary (secondary) power amplifier are described. The primary and secondary amplifiers operate as current sources providing current to the load. Capacitance coupling is used to couple the primary and secondary amplifier outputs. In some embodiments the combination of primary and secondary amplifiers achieve high average efficiency over the operating range of the device in which the primary and secondary amplifiers are used in combination as an amplifier device. The amplifier device is well suited for implementation using CMOS technology, e.g., N-MOSFETs, and can be implemented in an integrated circuit space efficient manner that is well suited for supporting RF transmissions in the GHz frequency range, e.g., 30 GHz frequency range. The primary amplifier in some embodiments is a CLASS-AB or B amplifier and the secondary amplifier is a CLASS-C amplifier.

A power amplifier includes: at least two first bridge type amplifying circuits and at least two second bridge type amplifying circuits; the negative pole of the first load of each first bridge type amplifying circuit is respectively coupled to the positive stage of the second load of each second bridge type amplifying circuits through a gating circuit. When both a first input signal input into one of the at least two first bridge type amplifying circuits and a second input signal input into one of the at least two second bridge type amplifying circuits are less than a preset threshold, the gating circuit is turned on, so that the one of the at least two first bridge type amplifying circuits and the one of the at least two second bridge type amplifying circuits can share load current by the gating circuit.

In one embodiment, a dual-mode power amplifier that can operate in different modes includes: a first pair of metal oxide semiconductor field effect transistors (MOSFETs) to receive and pass a constant envelope signal; a second pair of MOSFETs to receive and pass a variable envelope signal, where first terminals of the first pair of MOSFETs are coupled to first terminals of the second pair of MOSFETs, and second terminals of the first pair of MOSFETs are coupled to. second terminals of the second pair of MOSFETs; and a shared MOSFET stack coupled to the first pair of MOSFETs and the second pair of MOSFETs.

A power amplifier circuit includes amplifying transistors electrically cascade-connected, amplifying a signal supplied to a base, and outputting an amplified signal; a first resistive element having end parts connected to the base of a first amplifying transistor; a second resistive element having end parts connected to the base of a second amplifying transistor, which is an amplifying transistor located closer to an input side than the first amplifying transistor; a first bias supplying transistor having an emitter connected to one of the end parts of the first resistive element; a second bias supplying transistor having an emitter connected to one of the end parts of the second resistive element; and a bias current compensation transistor having a base connected to the end part of the first resistive element, a collector connected to the end part of the second resistive element, and an emitter connected to ground.

Examples disclosed herein relate to a high gain active relay antenna system. The active relay antenna system comprises a first antenna pair having a first receive antenna and a first transmit antenna to communicate wireless signals in a forward link from a base station to a plurality of users; and a second antenna pair having a second receive antenna and a second transmit antenna to communicate wireless signals in a return link from the plurality of users to the base station. The active relay antenna system further comprises a first active relay section and a second active relay section to provide for adjustable power gain in the wireless signals.

Various embodiments disclose a method and a device including: an antenna, a switching regulator, communication chip including an amplifier and a linear regulator operably connected to the amplifier and the switching regulator, the communication chip configured to transmit a radio-frequency signal from the electronic device through the antenna, and control circuitry configured to control the communication chip such that the linear regulator provides the amplifier with a voltage corresponding to an envelope of an input signal input to the amplifier, the input signal corresponding to the radio-frequency signal.

A power amplification device, including a first amplification branch, a second amplification branch, a harmonic injection circuit, and a first output matching circuit. A first amplifier in the first amplification branch supports a first frequency. A second amplifier in the second amplification branch supports the first frequency and a second frequency, and the second amplifier is turned off for a signal of the first frequency that has a power value lower than an enabling threshold. The harmonic injection circuit injects a signal of the second frequency that is input from a second input terminal (I2) to a signal of the first frequency that is input from a first input terminal (I1) to obtain a signal of the first frequency that has undergone harmonic injection.