A scalable periphery tunable matching power amplifier is presented. Varying power levels can be accommodated by selectively activating or deactivating unit cells of which the scalable periphery tunable matching power amplifier is comprised. Tunable matching allows individual unit cells to see a constant output impedance, reducing need for transforming a low impedance up to a system impedance and attendant power loss. The scalable periphery tunable matching power amplifier can also be tuned for different operating conditions such as different frequencies of operation or different modes.

A circuit topology including stacked power amplifiers (e.g., class D PA cells) in a ladder arranged in a house-of-cards topology such that the number of stacked-domains follows a decaying triangular series N, N1, N2, . . . , Ni from a fixed ladder to an i.sup.th ladder to provide a 1:(i+1) voltage conversion ratio, each stacked domain outputs its power via a flying domain power amplifier cell, and each ladder balances stacked domains of a prior ladder and combines power from all prior ladders.

A power amplifier, a radio remote unit (RRU), and a base station, where the power amplifier includes an envelope controller, a main power amplifier, and an auxiliary power amplifier. The main power amplifier and the auxiliary power amplifier both set an envelope voltage output by the envelope modulator as operating voltages, and because the operating voltages of the main power amplifier and the auxiliary power amplifier may be adjusted simultaneously, symmetry of the power amplifier is improved, and an efficiency loss occurring probability is low, thereby enhancing efficiency of the power amplifier.

A linearization circuit reduces intermodulation distortion in an amplifier that includes a first stage and a second stage. The linearization circuit receives a first signal that includes a first frequency and a second frequency and generates a difference signal having a frequency approximately equal to the difference of the first frequency and the second frequency, generates an envelope signal based at least in part on a power level of the first signal, and adjusts a magnitude of the difference signal based on the envelope signal. When the amplifier receives the first signal at an input terminal, the first stage receives the adjusted signal, and the second stage does not receive the adjusted signal, intermodulation between the adjusted signal and the first signal cancels at least a portion of the intermodulation between the first frequency and the second frequency from the output of the amplifier.

A linearization circuit that reduces intermodulation distortion in an amplifier output receives a first signal that includes a first frequency and a second frequency and generates a difference signal having a frequency approximately equal to the difference of the first frequency and the second frequency. The linearization circuit generates an envelope signal based at least in part on a power level of the first signal and adjusts a magnitude of the difference signal based on the envelope signal. When the amplifier receives the first signal at an input terminal and the adjusted signal at a second terminal, intermodulation between the adjusted signal and the first signal cancels at least a portion of the intermodulation products that result from the intermodulation of the first frequency and the second frequency.

Provided is a microphone system insensitive to external noise, and the microphone system includes a microphone sensor that generates sensing data by sensing a change in sound pressure through a sensor bias voltage, a lead-out circuit that provides the sensor bias voltage for operating the microphone sensor, removes noise of the sensing data, and outputs the sensing data, a first pad that connects the microphone sensor and the lead-out circuit to each other and allows the sensor bias voltage to pass therethrough, and a second pad that connects the microphone sensor and the lead-out circuit to each other and allows the sensing data to pass therethrough.

Circuits for power-combined power amplifier array are provided, the circuits comprising: an input splitter coupled to an input that provides a plurality of outputs; a plurality of power amplifier unit cells, each power amplifier unit cell coupled to a corresponding output of the input splitter and each power amplifier unit cell providing an output signal at an output of the power amplifier unit cell; and a power combiner having an output, a plurality of inputs, each input coupled to the output of a corresponding power amplifier unit cell, and a plurality of C-L-C-section equivalents, each having an input connected to a corresponding one of the plurality of inputs of the power combiner and an output connected to the output of the power combiner.

A digital power amplification circuit includes a decoding block configured to receive a first stream of digital codes and to derive from the first stream a second stream of digital codes, the decoding block including a decoder configured to decode the digital codes of the first stream and the second stream at a first clock rate, a main digital power amplifier configured to receive the decoded digital codes of the first stream, an upsampler configured to upsample the decoded digital codes of the second stream to a second clock rate that is greater than the first clock rate, an auxiliary digital power amplifier configured to receive the decoded digital codes of the second stream upsampled to the second clock rate, and a summer configured to sum (i) a main output signal of the main digital power amplifier and (ii) an auxiliary output signal of the auxiliary digital power amplifier.

A power amplifier circuit includes a first transistor amplifying a first signal; a second transistor amplifying a second signal; a bias circuit supplying a bias current or voltage to a base or gate of the second transistor; and an attenuator attenuating the first or second signal in accordance with a control voltage supplied from the bias circuit. The attenuator includes a first diode to which the control voltage is supplied, a third transistor including a collector connected to a supply path of the first or second signal, an emitter connected to a ground, and a base to which the control voltage is supplied from the first diode, and a capacitor connected in parallel with the first diode. The control voltage decreases as a second signal power level increases. The third transistor allows part of the first or second signal to pass to the emitter in accordance with the control voltage.

A device includes a substrate and a package input terminal. The device includes a driver amplifier mounted to the substrate and configured to receive a radio frequency input signal. A first amplifier is mounted to the substrate. The first amplifier includes a first amplifier input terminal. A second amplifier is mounted to the substrate. The second amplifier includes a second amplifier input terminal. An inter-stage network is connected between the driver amplifier and the first amplifier and between the driver amplifier and the second amplifier. The inter-stage network includes a first capacitor connected between the driver amplifier and the first amplifier input terminal, and an inductor having a first terminal and a second terminal. The first terminal of the inductor is connected to the first capacitor. The inter-stage network includes a second capacitor connected between the second terminal of the inductor and the second amplifier input terminal.