An RF amplifier includes an amplifier chip on a flange having an input and an output comprising a parasitic capacitance and a parasitic inductance, a first chip capacitor coupled to the output of the output of the amplifier by a first plurality of bond wires, and a second chip capacitor coupled to the first chip capacitor by a second plurality of bond wires, and an output impedance matching network having an input coupled to the output of the second chip capacitor by a third plurality of bond wires, and an output, and a phase shift between the input and the output of less than 90 degrees, wherein the phase shift from the output of the amplifier chip to the output of the output impedance matching network is 180 degrees.

Diversity receiver front end system with methods for improving signal processing using tunable matching circuits. The methods can include tuning impedance matching circuits based on frequency bands. For a first path, an impedance can be provided that reduces an in-band noise figure, increases an in-band gain, decreases an out-of-band noise figure, and/or decreases an out-of-band gain. In this way, signals propagated along selectively activated paths between an input of a receiving system and an output of the receiving system can be improved. The signals can be amplified using amplifiers disposed on corresponding paths between the input and output of the receiving system.

A first branch group circuit includes a first branch circuit receiving a first RF input signal and first control information; and a second branch circuit receiving the first input signal and second control information. Each of the first and second branch circuits includes a power amplifier. The second control information enables the second branch circuit to be switched on or off while the first branch circuit remains on. A second branch group circuit includes: a third branch circuit receiving a second RF input signal and third control information; and a fourth branch circuit receiving the second input signal and fourth control information. Each of the third and fourth branch circuits includes a power amplifier. The fourth control information enables the fourth branch circuit to be switched on or off while the third branch circuit remains on. A combiner combines output signals of the power amplifiers to produce an output signal.

A radio frequency (RF) power transistor circuit includes a power transistor and at least one decoupling circuit. The power transistor has a control electrode coupled to an input terminal for receiving an RF input signal, and a current electrode for providing an RF output signal at an output terminal. A decoupling circuit is coupled between the control electrode and a ground terminal, and/or between the current electrode and the ground terminal. The decoupling circuit includes a resistor coupled in series with components of a resonant circuit having a resonance that is lower than an RF frequency (e.g., lower than 20 megahertz). The resistor is for dampening the resonance of the resonant circuit.

An energy absorbing circuit includes a power divider that is configured to divide an incoming RF signal into a plurality of RF component signals; a plurality of transmission lines that are connected with the power divider, each of the transmission lines configured to transmit a respective RF component signal of the plurality of RF component signals; and a plurality of matching elements, each matching element being terminated to a respective one of the transmission lines.

The present disclosure provides an amplifier circuit that includes one or more amplifier stages, each of the one or more amplifier stages including a complementary transistor configuration. The complementary transistor configuration includes an NMOS transistor and a PMOS transistor. The NMOS transistor is electrically coupled in parallel to the PMOS transistor. The amplifier circuit further includes an output amplifier stage electrically coupled to an output of the one or more amplifier stages, the output amplifier stage including a non-complementary transistor configuration including one or more NMOS transistors or PMOS transistors.

A spacecraft includes a payload subsystem including a plurality of transmit antenna feeds, a digital channelizer, and a power amplification arrangement including a plurality of power amplifiers. The power amplification arrangement has at least one input communicatively coupled with an output of the digital channelizer and at least one output communicatively coupled with at least one of the plurality of transmit antenna feeds. A processor is configured to control the digital channelizer, and to adjust a saturated output power of at least one power amplifier of the plurality of power amplifiers in the power amplification arrangement.

Circuits and methods related to power amplifiers. In some implementations, a bias circuit includes a reference device connectable to receive a first electrical supply level, the reference device arranged to produce an electrical bias condition using the first electrical supply level, and the reference device connectable to provide the electrical bias condition to an amplifier device connectable to a second electrical supply level. The bias circuit also includes a differential amplifier connectable to receive the first electrical supply level, the differential amplifier having a first input connectable to a first node of the reference device and a second input connectable to receive a reference electrical level, the differential amplifier arranged to maintain a first electrical level on the first node of the reference device as a function of the reference electrical level.

High-data rate channel interface modules and equalization methods employing a finite impulse response (FIR) analog receive filter. Embodiments include an illustrative channel interface module having multiple amplifier-based delay units arranged in a sequential chain to convert an analog input signal into a set of increasingly-delayed analog signals that are weighted and combined together with the analog input signal to form an equalized signal; and a symbol decision element operating on the equalized signal to obtain a sequence of symbol decisions. An interface that extracts received data from the sequence of symbol decisions. The delay units may employ one or more delay cells each having a common-source amplifier stage followed by a source follower output stage, the two stages providing approximately equal portions of the propagation delay. An enhanced gate-to-drain capacitance in the common-source amplifier may increase propagation delay while reducing bandwidth limitations.

Apparatus and methods for regulated voltage distribution are disclosed. Distribution elements can pass a regulated voltage provided by a single voltage regulator to thereby distribute the regulated voltage. A distribution element of the distribution elements can be included in a feedback path that provides a feedback signal to an input of the voltage regulator. The voltage regulator can be a low dropout voltage regulator, for example. The regulated voltage can be used in a variety of applications, for example, as a bias voltage for a power amplifier.