The present technology relates to an amplifier, an audio signal output method, and an electronic device that can inhibit unintended sound output in a class D amplifier that changes a peak value of a PWM signal. The amplifier includes: a positive-side amplitude generating circuit configured to generate positive-side amplitude of an output PWM signal that is a PWM signal to be output outside an apparatus; a negative-side amplitude generating circuit configured to generate negative-side amplitude of the output PWM signal; and a feedback circuit configured to feed back a difference between the amplitude generated by the positive-side amplitude generating circuit and the amplitude generated by the negative-side amplitude generating circuit to the positive-side amplitude generating circuit and the negative-side amplitude generating circuit. The present technology is applicable, for example, to an amplifier or the like of an electronic device such as an audio player.

An embodiment of a Doherty amplifier module includes a substrate, a first amplifier die, and a second amplifier die. The first amplifier die includes one or more first power transistors configured to amplify, along a first signal path, a first input RF signal to produce an amplified first RF signal. The second amplifier die includes one or more second power transistors configured to amplify, along a second signal path, a second input RF signal to produce an amplified second RF signal. The first and second amplifier die each also include an elongated output pad that is configured to enable a pluralities of wirebonds to be connected in parallel along the length of the elongated output pad so that the pluralities of wirebonds extend in perpendicular directions to the first and second signal paths.

A power amplification module includes: a first transistor that amplifies a first radio frequency signal and outputs a second radio frequency signal; a second transistor that amplifies the second radio frequency signal and outputs a third radio frequency signal; and first and second bias circuits that supply first and second bias currents to bases of the first and second transistors. The first bias circuit includes a third transistor that outputs the first bias current from its emitter or source, a capacitor that is input with the first radio frequency signal and connected to the base of the first transistor, a first resistor connected between the emitter or source of the third transistor and the base of the first transistor, a second resistor connected between the capacitor and the emitter or source of the third transistor, and a third resistor connected between the capacitor and the base of the first transistor.

Disclosed herein are signal amplifiers that have an input impedance that varies over different bias currents. The signal amplifier includes a gain stage with a plurality of switchable amplification branches that are each capable of being activated such that one or more of the activated amplification branches provides a targeted adjustment to the input impedance. In addition, disclosed herein are signal amplifiers that have a variable-gain stage configured to provide a plurality of gain levels that result in different input impedance values presented to a respective signal by the variable-gain stage. The variable-gain stage can include a plurality of switchable amplification branches that provide a targeted adjustment to the respective input impedance values. The variable-gain stage can include a plurality of switchable inductive elements that are configured to be activated to provide a targeted adjustment to the respective input impedance values.

Cascode power amplifier with voltage limiter. A power amplification system can include an input transistor having an input transistor gate configured to receive a radio-frequency (RF) signal, an input transistor source coupled to a ground voltage, and an input transistor drain. The power amplification can further include an output transistor having an output transistor drain configured to output an amplified version of the RF signal, an output transistor gate coupled to a bias voltage, and an output transistor source. The power amplification system can further include a high voltage limiter coupled between the output transistor drain and output transistor gate. The high voltage limiter can be configured to prevent a gate-drain voltage of the output transistor from exceeding a high voltage threshold.

A high-frequency power amplifier is configured to include plural island patterns (28) in which ends thereof are arranged in the vicinity of a transmission line (23) and other ends thereof are arranged in the vicinity of an end line (24a) in a transmission line (24), a wire (30) for connecting an end of an island pattern (28) and the transmission line (23), and a wire (31) for connecting another end of the island pattern (28) and the end line (24a) of the second transmission line (24), so that a mismatch of the impedance component having a resistance component and a reactance component can be compensated for by changing the number of first connecting members and the number of second connecting members, the first and second connecting members configured to connect an island pattern (28) to the transmission lines (23) and (24).

A power amplifier cell comprising a first power amplifier, a second power amplifier and a balun. The balun comprises a first inductor and a second inductor that define a first transformer; and a third inductor and a fourth inductor that define a second transformer. The following: (i) a parasitic capacitance of the first power amplifier; (ii) a leakage inductance of the first transformer; and (iii) a capacitive coupling between the first inductor and the second inductor, contribute to a first impedance matching circuit for the first power amplifier. Also, the following (iv) a parasitic capacitance of the second power amplifier; (v) a leakage inductance of the second transformer; and (vi) a capacitive coupling between the third inductor and the fourth inductor, contribute to a second impedance matching circuit for the second power amplifier.

A variable load power amplifier that improves the performance of a power amplifier that provides both envelope tracking (ET) and average power tracking (APT). The variable load power amplifier can include a plurality of amplifiers that are each selectively connectable into one of a plurality of parallel combinations, each of the plurality of parallel combinations characterized by a corresponding load line. The variable load power amplifier can also include a plurality of control elements arranged to selectively connect one or more of the plurality of amplifiers into one of the plurality of parallel combinations, each of the plurality of control elements having a respective input terminal provided to receive a respective control signal, each of the plurality of control elements responsive to the respective control signal.

A radio-frequency (RF) power amplifier includes a matching network comprising at least one matching network circuit corresponding to at least one symmetry node, at least one detector for detecting power of a detected signal at the symmetry node of the matching network, and generating at least one control signal according to the power of the detected signal, wherein the detected signal is an odd harmonic of an RF signal when the RF power amplifier operates in a differential mode or an even harmonic of the RF signal when the RF power amplifier operates in a common mode, and at least one adjusting circuit for adjusting the RF signal according to the at least one control signal.

A class D amplifier receives and amplifies a differential analog signal which is then differentially integrated. Two pulse width modulators generate pulse signals corresponding to the differentially integrated analog signal and two power units generate output pulse signals. The outputs the power units are coupled to input terminals of integrators via a resistor feedback network. An analog output unit converts the pulse signals to an output analog signal. The differential integration circuitry implements a soft transition between mute/un-mute. In mute, the integrator output is fixed. During the soft transition, the PWM outputs change slowly from a fixed 50% duty cycle to a final value to ensure that no pop noise is present in the output as a result of mode change.