Metal pillars are placed adjacent to transistor arrays in the power amplifiers that can be used in wireless devices. By placing the metal pillars in intimate contact with the silicon substrate and not over a substantial portion of the transistor arrays, the heat generated by the transistor arrays flows down into the silicon substrate and out the metal pillar. The metal pillar forms a solder bump of a flip chip power amplifier die, which when soldered to a module, further conducts the heat away from the transistor array.

In some embodiments, a power amplification system can include a common base amplifier configured to amplify an input signal received at an input node to generate an intermediate signal at an intermediate node. The power amplification system can further include a power amplifier configured to amplify the intermediate signal received at the intermediate node to generate an output signal at an output node.

A power splitter that amplifies an input radio-frequency (RF) signal. The power splitter uses a single transistor in a common emitter stage of a cascode amplifier and two or more common base stages of the cascode amplifier to amplify and to split the input RF signal. A common base biasing signal can be used to simultaneously enable two or more of the common base stages to generate two or more amplified RF output signals.

An amplification apparatus includes: a signal splitter for splitting an input radio frequency signal and outputting the resulting split radio frequency signals; a plurality of amplifier units for amplifying the radio frequency signals outputted from the signal splitter, the amplifier units being disposed circularly to form a generally cylindrical shape; a plurality of water cooling heat sinks disposed circularly at positions corresponding to the positions of the plurality of amplifier units so as to cool the plurality of amplifier units by cooling water; and a signal combiner for combining the radio frequency signals outputted from the plurality of amplifier units, respectively, and outputting the resulting combined radio frequency signal.

A transformer has a first winding, a second winding and a third winding. The first winding is configured to receive a first signal. The second winding is magnetically coupled to the first winding and configured to generate a second signal through electromagnetic induction with the first winding, or by receiving a second input signal. The third winding is magnetically coupled to the second winding, magnetically isolated from the first winding, and configured to generate a third signal through electromagnetic induction with the second winding. The second winding is posited between the first winding and the third winding. The first winding is posited adjacent to the second winding, and the second winding is posited adjacent to the third winding.

A device (e.g., a Doherty amplifier) housed in an air cavity package includes one or more isolation structures over a surface of a substrate and defining an active circuit area. The device also includes first and second adjacent circuits within the active circuit area, first and second leads coupled to the isolation structure(s) between opposite sides of the package and electrically coupled to the first circuit, third and fourth leads coupled to the isolation structure(s) between the opposite sides of the package and electrically coupled to the second circuit, a first terminal over the first side of the package between the first lead and the third lead, a second terminal over the second side of the package between the second lead and the fourth lead, and an electronic component coupled to the package and electrically coupled to the first terminal, the second terminal, or both the first and second terminals.

An envelope tracking (ET) current bias circuit comprises an envelope detection circuit detecting an ET voltage from an input signal; a first voltage/current converting circuit converting a reference voltage into a direct current (DC) current and adjusting the DC current according to a first control signal; a second voltage/current converting circuit converting the ET voltage into an ET current, adjusting the ET current according to a second control signal, and removing a DC offset current from the ET current to provide an offset compensated ET current; and an arithmetic circuit calculating levels of the offset compensated ET current and the DC current to generate an ET bias current.

A gate bias circuit for a plurality of GaAs amplifier stages is a transistor coupled to a temperature compensation current received from a CMOS control stage. A plurality of pHEMPT amplifier stages are coupled to the gate bias circuit and to a control voltage which switches the amplifier stage. A selectively controlled stage pass transistor enables a current mirror between the gate bias circuit and each stage amplifying transistor. The penultimate pHEMPT amplifier stage is coupled to a CMOS amplifier. A CMOS circuit provides both the temperature compensation current by a proportional to absolute temperature (PTAT) circuit and the control voltage enabling each pHEMPT transistor to receive its input signal in combination with the gate bias voltage.

An apparatus for detecting difference in operating characteristics of a main circuit by using a replica circuit is presented. In one exemplary case, a sensed difference in operating characteristics of the two circuits is used to drive a tuning control loop to minimize the sensed difference. In another exemplary case, several replica circuits of the main circuit are used, where each is isolated from one or more operating variables that affect the operating characteristic of the main circuit. Each replica circuit can be used for sensing a different operating characteristic, or, two replica circuits can be combined to sense a same operating characteristic.

Embodiments of the disclosure relate to a multi-mode power management system supporting fifth-generation new radio (5G-NR). The multi-mode power management system includes first tracker circuitry and second tracker circuitry each capable of supplying an envelope tracking (ET) modulated or an average power tracking (APT) modulated voltage. In examples discussed herein, the first tracker circuitry and the second tracker circuitry have been configured to support third-generation (3G) and fourth-generation (4G) power amplifier circuits in various 3G/4G operation modes. The multi-mode power management system is adapted to further support a 5G-NR power amplifier circuit(s) in various 5G-NR operation modes based on the existing first tracker circuitry and/or the existing second tracker circuitry. In this regard, the 5G-NR power amplifier circuit(s) can be incorporated into the existing multi-mode power management system with minimum hardware changes, thus enabling 5G-NR support without significantly increasing component count, cost, and footprint of the multi-mode power management system.