A radio frequency (RF) power transistor circuit includes a power transistor and a decoupling circuit. The power transistor has a control electrode coupled to an input terminal for receiving an RF input signal, a first current electrode for providing an RF output signal at an output terminal, and a second current electrode coupled to a voltage reference. The decoupling circuit includes a first inductive element, a first resistor, and a first capacitor coupled together in series between the first current electrode of the power transistor and the voltage reference. The decoupling circuit is for dampening a resonance at a frequency lower than an RF frequency.

An output network connected to an output of a nonlinear unmatched power amplifier that provides an amplified voltage signal at a fundamental frequency. The output network includes multiple acoustic resonators configured to match multiple harmonic frequencies of the amplified voltage signal to one of substantially zero impedance, appearing as a short, or substantially infinite impedance, appearing as an open, resulting in zero voltage or zero current, respectively, to avoid power distribution at the higher harmonic frequencies. Each higher harmonic frequency is higher than a first harmonic frequency of the multiple harmonic frequencies, which is a fundamental frequency.

A multi-level, multi-branch outphasing amplifier (20-1) includes a first branch group circuit (22-1) including a first branch circuit (11) receiving a first RF input signal (S.sub.1(t)) and first control information (S.sub.11.sub._Ctrl=V.sub.DD) and a second branch circuit (12) receiving the first input signal and second control information (S.sub.12.sub._Ctrl). Each of the first (11) and second (12) branch circuits includes a power amplifier. The second control information enables the second branch circuit to be switched on or off while the first branch circuit (12) remains on. A second branch group circuit (22-2) includes a third branch circuit (21) receiving a second RF input signal (S.sub.2(t)) and third control information (S.sub.21.sub._Ctrl=V.sub.DD) and a fourth branch circuit (22) receiving the second input signal (S.sub.2(t)) and fourth control information (S.sub.22.sub._Ctrl). Each of the third and fourth branch circuits includes a power amplifier. The fourth control information enables the fourth branch circuit to be switched on or off while the third branch circuit remains on. A combiner (24) combines output signals of the power amplifiers to produce an output signal (S.sub.OUT(t)).

A dual-mode envelope tracking (ET) power management circuit is provided. An ET amplifier(s) in the dual-mode ET power management circuit is capable of supporting normal-power user equipment (NPUE) mode and high-power user equipment (HPUE) mode. In the NPUE mode, the ET amplifier(s) amplifies a radio frequency (RF) signal(s) to an NPUE voltage based on a supply voltage for transmission in an NPUE output power. In the HPUE mode, the ET amplifier(s) amplifies the RF signal(s) to an HPUE voltage higher than the NPUE voltage based on a boosted supply voltage higher than the supply voltage for transmission in an HPUE output power higher than the NPUE output power. The ET amplifier(s) maintains a constant load line between the NPUE mode and the HPUE mode. By maintaining the constant load line, it is possible to maintain efficiency of the ET amplifier(s) in both the NPUE mode and the HPUE mode.

A class D amplifier receives and amplifies a differential analog signal which is then differentially integrated. Two pulse width modulators generate pulse signals corresponding to the differentially integrated analog signal and two power units generate output pulse signals. The outputs the power units are coupled to input terminals of integrators via a resistor feedback network. An analog output unit converts the pulse signals to an output analog signal. The differential integration circuitry implements a soft transition between mute/un-mute. In mute, the integrator output is fixed. During the soft transition, the PWM outputs change slowly from a fixed 50% duty cycle to a final value to ensure that no pop noise is present in the output as a result of mode change.

An output network connected to an output of a nonlinear unmatched power amplifier that provides an amplified voltage signal at a fundamental frequency. The output network includes multiple acoustic resonators configured to match multiple harmonic frequencies of the amplified voltage signal to one of substantially zero impedance, appearing as a short, or substantially infinite impedance, appearing as an open, resulting in zero voltage or zero current, respectively, to avoid power distribution at the higher harmonic frequencies. Each higher harmonic frequency is higher than a first harmonic frequency of the multiple harmonic frequencies, which is a fundamental frequency.

Metal pillars are placed adjacent to NPN transistor arrays that are used in the power amplifier for RF power generation. By placing the metal pillars in intimate contact with the silicon substrate, the heat generated by the NPN transistor arrays flows down into the silicon substrate and out the metal pillar. The metal pillar also forms an electrical ground connection in close proximity to the NPN transistors to function as a grounding point for emitter ballast resistors, which form an optimum electrothermal configuration for a linear SiGe power amplifier.

A surface acoustic wave (SAW) filter that receives an aggregate circuit and outputs two or more sub-signals on outputs each of a different frequency band. The sub-signals are amplified by low noise amplifiers and, in one implementation, the amplified sub-signals can be summed. The outputs are connected via a switched passive network so that portions of the sub-signals on the outputs that are not in the selected frequency band are at least partially terminated.

Systems and methods that cancel distortion in the amplified outputs of a node by equalizing the distortion characteristics amplifiers in the node, so as to improve the effectiveness of predistortion applied to a downstream signal amplified by the node.

A system and method for packaging a semiconductor device that includes a wall to reduce electromagnetic coupling is presented. A semiconductor device has a substrate on which a first circuit and a second circuit are formed proximate to each other. An isolation wall of electrically conductive material is located between the first circuit and the second circuit, the isolation wall being configured to reduce inductive coupling between the first and second circuits during an operation of the semiconductor device. Several types of isolation walls are presented.