A peaking amplifier is disclosed. The peaking amplifier includes a driver stage, a final stage, and an interstage matching network. The driver stage has a load impedance and is configured to generate a driver output based on an input signal. The final stage has a final stage input impedance and is configured to generate a peaking output based on the driver output. The interstage matching network is coupled to the driver stage and the final stage. The interstage matching network is configured to transform the final stage input impedance to the load impedance for the driver stage when the peaking amplifier is ON and to provide a short to an input of the final stage when the peaking amplifier is in an OFF state.

Embodiments of the disclosure relate to a multi-mode power management system supporting fifth-generation new radio (5G-NR). The multi-mode power management system includes first tracker circuitry and second tracker circuitry each capable of supplying an envelope tracking (ET) modulated or an average power tracking (APT) modulated voltage. In examples discussed herein, the first tracker circuitry and the second tracker circuitry have been configured to support third-generation (3G) and fourth-generation (4G) power amplifier circuits in various 3G/4G operation modes. The multi-mode power management system is adapted to further support a 5G-NR power amplifier circuit(s) in various 5G-NR operation modes based on the existing first tracker circuitry and/or the existing second tracker circuitry. In this regard, the 5G-NR power amplifier circuit(s) can be incorporated into the existing multi-mode power management system with minimum hardware changes, thus enabling 5G-NR support without significantly increasing component count, cost, and footprint of the multi-mode power management system.

Embodiments of circuits for use with an amplifier that includes multiple amplifier paths include a first circuit and a second circuit in parallel with the first circuit. The first circuit includes a first input coupled to a first power divider output, a first output coupled to a first amplifier path of the multiple amplifier paths, and a first adjustable phase shifter and a first attenuator series coupled between the first input and the first output. The second circuit includes a second input coupled to a second power divider output, a second output coupled to a second amplifier path of the multiple amplifier paths, and a second adjustable phase shifter coupled between the second input and the second output.

An e-band transceiver includes a transmitter circuit and a receiver circuit. The transmitter circuit includes a surface mounted technology (SMT) module on which is mounted a silicon-germanium (SiGe) bipolar plus CMOS (BiCMOS) converter, a gallium arsenide (GaAs) pseudomorphic high-electron-mobility transistor (pHEMT) output amplifier coupled to the SiGe BiCMOS converter, and a microstrip/waveguide interface coupled to the GaAs pHEMT output amplifer. The receiver circuit of the e-band transceiver includes a receiver-side SMT module on which is mounted a receiver-side SiGe BiCMOS converter, a GaAs pHEMT low noise amplifier coupled to the receiver-side SiGe BiCMOS converter, and a receiver-side microstrip/waveguide interface coupled to the receiver-side GaAs pHEMT low noise amplifier.

A linearization circuit that reduces intermodulation distortion in an amplifier output receives a first signal that includes a first frequency and a second frequency and generates a difference signal having a frequency approximately equal to the difference of the first frequency and the second frequency. The linearization circuit generates an envelope signal based at least in part on a power level of the first signal and adjusts a magnitude of the difference signal based on the envelope signal. When the amplifier receives the first signal at an input terminal and the adjusted signal at a second terminal, intermodulation between the adjusted signal and the first signal cancels at least a portion of the intermodulation products that result from the intermodulation of the first frequency and the second frequency.

A radio frequency filter includes communication bandpass filters disposed corresponding respectively to a plurality of communication bands, a switch, and a matching circuit. The switch includes a common terminal and a plurality of optionally selectable terminals, the plurality of optionally selectable terminals being individually connected to the plurality of bandpass filters in a one-to-one relation. The matching circuit is connected to the common terminal and is a common matching circuit to the plurality of communication bandpass filters. The plurality of communication bandpass filters are set such that filter characteristics of a serial circuit in combination of one of the plurality of communication bandpass filters, the one being selected by the switch, and the common matching circuit are improved in comparison with filter characteristics of the selected communication bandpass filter with respect to the communication band corresponding to the selected communication bandpass filter.

A power amplifier circuit includes: a first differential amplifier that amplifies a first signal split from the input signal and outputs a second signal; a second differential amplifier that amplifies a third signal split from the input signal and outputs a fourth signal; a first transformer including a first input-side winding to which the second signal is input and a first output-side winding; a second transformer including a second input-side winding to which the fourth signal is input and a second output-side winding; a first phase conversion element that is connected in parallel with the first output-side winding and outputs a fifth signal; and a second phase conversion element that is connected in parallel with the second output-side winding and outputs a sixth signal. The first and second output-side windings are connected in series and output a signal obtained by adding voltages of the fifth and sixth signals together.

A gate bias circuit for a plurality of GaAs amplifier stages is a transistor coupled to a temperature compensation current received from a CMOS control stage. A plurality of pHEMPT amplifier stages are coupled to the gate bias circuit and to a control voltage which switches the amplifier stage. A selectively controlled stage pass transistor enables a current mirror between the gate bias circuit and each stage amplifying transistor. The penultimate pHEMPT amplifier stage is coupled to a CMOS amplifier. A CMOS circuit provides both the temperature compensation current by a proportional to absolute temperature (PTAT) circuit and the control voltage enabling each pHEMPT transistor to receive its input signal in combination with the gate bias voltage.

A radio-frequency module comprises a low-noise amplifier including a common source transistor having a gate node that receives a radio-frequency input signal and a drain node that transmits a combined radio-frequency output signal, and a correction signal input path configured to receive a correction signal and provide the correction signal to a source node of the common source transistor to generate, at least in part, the combined radio-frequency output signal.

A Digital power amplifier (13) to drive an RFID antenna (10) with a substantial sinusoidal output current (I) which digital power amplifier (13) comprises: an integrated circuit (IC2) with a first transmission output pin (15) and a second transmission output pin (16) to provide an output signal (17); an adaption circuit (14) of discrete components (C2a, C2b) connected to the first and second transmission output pin (15, 16) to adapt the output signal (17) and feed the substantial sinusoidal output current (I) with a transmission resonance frequency to the RFID antenna (10), wherein the integrated circuit (IC2) comprises: a digital control section (19) with a number of N wave-forming contacts (20) to output a digital wave-forming bit combination of N bits with a clock frequency M-times the transmission resonance frequency; a number of N driver blocks (21) each connected with a first contact (22) to one of the wave-forming contacts (20) and a number of N/2 of them connected with a second contact to the first transmission output pin (15) and the other number of N/2 of them connected with their second contact to the second transmission output pin (16), which driver blocks (21) are built to provide increments of the substantial sinusoidal output current (I) to the first and second transmission output pin (15, 16).