A radio frequency (RF) power transistor circuit includes a power transistor and a decoupling circuit. The power transistor has a control electrode coupled to an input terminal for receiving an RF input signal, a first current electrode for providing an RF output signal at an output terminal, and a second current electrode coupled to a voltage reference. The decoupling circuit includes a first inductive element, a first resistor, and a first capacitor coupled together in series between the first current electrode of the power transistor and the voltage reference. The decoupling circuit is for dampening a resonance at a frequency lower than an RF frequency.

An apparatus includes: an input coupler configured to receive an input voltage and output a first coupled voltage and a second coupled voltage in accordance with a first bias voltage and a second bias voltage, respectively; a stacked amplifier pair configured to receive the first coupled voltage and the second coupled voltage and output a first output voltage and a second output voltage in accordance with a first DC voltage, a second DC voltage, and a third DC voltage; and an output combiner configured to establish a combined output voltage in accordance with a combination of the first output voltage and the second output voltage, wherein the stacked amplifier pair includes a first amplifier operating with a power supplied from the second DC voltage to the first DC voltage and a second amplifier operating with a power supplied from the third DC voltage to the second DC voltage.

A power amplifier module includes an amplifier that amplifies an input signal and outputs an amplified signal, an emitter follower transistor that supplies a bias signal to the amplifier to control a bias point of the amplifier, and a current source that supplies a control current which changes in accordance with a change in control voltage to a collector of the emitter follower transistor. The current source limits the control current to not greater than an upper limit.

Circuits and methods for 2G amplification using 3G/4G linear path combination. In some embodiments, a front-end architecture can include a first amplification path and a second amplification path, with each being configured to amplify a 3G/4G signal, and the first amplification path including a phase shifting circuit. The front-end architecture can further include a splitter configured to receive a 2G signal and split the 2G signal into the first and second amplification paths, and a combiner configured to combine amplified 2G signals from the first and second amplification paths into a common output path. The front-end architecture can further include an impedance transformer implemented along the common output path to provide a desired impedance for the combined 2G signal.

A millimeter (mm) wave power amplifier includes a plurality of amplifiers, each amplifier including an amplifying FET including a gate, drain and source. The mm wave power amplifier also includes an input port, an output port, a VDS port being connected to a VDS voltage source for setting the drain-source voltage of the FET, and a VGS port being connected to a VGS voltage source for setting the gate-source voltage of the FET. The output ports of the amplifiers are connected to a signal combiner and the input ports of the amplifiers are connected to a signal splitter. At least one of (a) at least two of the VGS ports are connected to different VGS voltage sources, and (b) at least two of the VDS ports are connected to different VDS voltage sources.

An apparatus, comprising has an array of power amplifiers. A power detector collects a power signal applied to the array of power amplifiers. Digital logic is connected to the array of power amplifiers and the power detector. The digital logic is configured to evaluate the power signal and select an array pattern from a set of array patterns and generate a control signal to implement the array pattern on the array of power amplifiers. Each array pattern in the set of array patterns includes at least one operative power amplifier.

Diversity receiver for wireless applications. In some embodiments, a receiver system can include a controller configured to selectively activate one or more of a plurality of paths between an input and an output, and a plurality of amplifiers, with each one of the plurality of amplifiers disposed along a corresponding one of the plurality of paths and configured to amplify a signal received at the amplifier. The receiving system can further include two or more of features including (a) variable-gain amplifiers, (b) phase-shifting components, (c) impedance matching components, (d) post-amplifier filters, (e) a switching network, and (f) flexible band routing. In some embodiments, such a receiving system can be implemented as a diversity receive module.

Front-end integrated circuit for wireless local area network WLAN applications. In some embodiments, a semiconductor die can include a semiconductor substrate, and a power amplifier implemented on the semiconductor substrate and configured for WLAN transmit operation associated with a frequency range. The semiconductor die can further include a low-noise amplifier (LNA) implemented on the semiconductor substrate and configured for WLAN receive operation associated with the frequency range. The semiconductor die can further include a transmit/receive switch implemented on the semiconductor substrate and configured to facilitate the transmit and receive operations.

Embodiments of radio frequency (RF) systems include a transmit/receive switch integrated with one or more power amplifiers and/or other components. The power amplifiers can have transformer-based architectures. A compensation circuit can act to protect the receive path during an RF transmit mode.

Systems, methods and apparatus for practical realization of an integrated circuit comprising a stack of transistors operating as an RF amplifier are described. As stack height is increased, capacitance values of gate capacitors used to provide a desired distribution of an RF voltage at the output of the amplifier across the stack may decrease to values approaching parasitic/stray capacitance values present in the integrated circuit which may render the practical realization of the integrated circuit difficult. Coupling of an RF gate voltage at the gate of one transistor of the stack to a gate of a different transistor of the stack can allow for an increase in the capacitance value of the gate capacitor of the different transistor for obtaining an RF voltage at the gate of the different transistor according to the desired distribution.