An integrated circuit chip includes a first single-ended-to-differential amplifier configured to generate a differential output associated with an input of said first single-ended-to-differential amplifier; a second single-ended-to-differential amplifier arranged in parallel with said first single-ended-to-differential amplifier; a first set of switch circuits arranged downstream of said first single-ended-to-differential amplifier; a second set of switch circuits arranged downstream of said second single-ended-to-differential amplifier; and a first differential-to-single-ended amplifier arranged downstream of a first one of said switch circuits in said first set and downstream of a first one of said switch circuits in said second set.

A transformer includes: a primary winding comprising a first port, a second port and a metal layer connected between the first port and the second port, the metal layer comprising a plurality of sections of different electrical lengths and/or characteristic impedances; and a secondary winding electromagnetically coupled with the primary winding, the secondary winding comprising a first port, a second port and a metal layer connected between the first port and the second port, the metal layer comprising a plurality of sections of different electrical lengths and/or characteristic impedances.

A radio frequency power amplifier (RF PA) apparatus includes a first RF PA, a second RF PA, and a controller. The first RF PA is configured to deliver RF power to a load over a first range of RF power levels. The second RF PA is configured to deliver RF power to the load over a second range of RF power levels greater than the first range of RF power levels. The controller controls whether the first RF PA is delivering RF power to the load or the second RF PA is delivering RF power to the load, and is further configured to coordinate and control handoffs between the first and second RF PAs by varying magnitudes of input RF voltages applied to the RF input ports of the first and second RF PAs or by varying magnitudes of input bias voltages applied to the RF input ports of the first and second RF PAs.

A temperature correction circuit and method for maintaining a transistor of a power amplifier in a linear operating region of the transistor. The temperature correction circuit includes a first current source circuit operable to provide a first correction current proportional to an absolute temperature of a semiconductor die including the transistor. The temperature correction circuit also includes a second current source circuit operable to provide a second correction current proportional to a change in temperature of a part of the semiconductor die in which the transistor is located during operation of the transistor. The temperature correction circuit further includes a third current source circuit operable to provide a gain selection current. The temperature correction circuit also includes circuitry for producing a reference current from the first and second correction currents and the gain current. The temperature correction circuit further includes an output for providing the reference current to the transistor.

A radio frequency (RF) transmitter includes a power amplifier comprising a plurality of power amplifier cells. At least one digital signal processing module of the RF transmitter is operably coupled to the power amplifier and comprises at least one digital pre-distortion component arranged to apply at least one digital pre-distortion codeword to the plurality of power amplifier cells, wherein the at least one digital pre-distortion codeword is applied to at least one of the plurality of power amplifier cells via a digital filter. A combiner is arranged to combine outputs of the plurality of power amplifier cells thereby generating an analogue RF signal for transmission over an RF interface based at least partly on the digitally filtered at least one digital pre-distortion codeword.

A voltage clamping circuit is provided. In an embodiment, the voltage clamping circuit includes a plurality of gain shifting circuits and a signal processing circuit. The plurality of gain shifting circuits receive an input voltage and voltage levels to generate a plurality of shifted voltages. The signal processing circuit generates a difference value of the plurality of shifted voltages to generate an output voltage according to the difference value, such that the voltage clamping circuit achieves an implementation of a passing band or a rejection of the input voltage.

Methods and systems for vector combining power amplification are disclosed herein. In one embodiment, a plurality of signals are individually amplified, then summed to form a desired time-varying complex envelope signal. Phase and/or frequency characteristics of one or more of the signals are controlled to provide the desired phase, frequency, and/or amplitude characteristics of the desired time-varying complex envelope signal. In another embodiment, a time-varying complex envelope signal is decomposed into a plurality of constant envelope constituent signals. The constituent signals are amplified equally or substantially equally, and then summed to construct an amplified version of the original time-varying envelope signal. Embodiments also perform frequency up-conversion.

Devices and methods related to embedded sensors for dynamic error vector magnitude corrections. In some embodiments, a power amplifier (PA) can include a PA die and an amplification stage implemented on the PA die. The amplification stage can include an array of amplification transistors, with the array being configured to receive and amplify a radio-frequency (RF) signal. The PA can further include a sensor implemented on the PA die. The sensor can be positioned relative to the array of amplification transistors to allow sensing of an operating condition representative of at least some of the amplification transistors. The sensor can be substantially isolated from the RF signal.

Aspects of this disclosure relate to bulk acoustic wave components. A bulk acoustic wave component can include a substrate, at least one bulk acoustic wave resonator on the substrate, and a cap enclosing the at least one bulk acoustic wave resonator. The cap can include a sidewall spaced apart from an edge of the substrate. The sidewall can be 5 microns or less from the edge of the substrate.

An amplifier arrangement comprises N amplifier stages (10.sub.1 to 10.sub.N), wherein N is an integer equal or greater than four. The amplifier arrangement comprises a cascade of quarter wavelength transmission lines coupled between an output of an amplifier of a first amplifier stage (10.sub.1) and an output node (15) of the amplifier arrangement, wherein the cascade comprises N−1 quarter wavelength transmission lines (11.sub.1 to 11.sub.N−1). An amplifier of the Nth stage (10.sub.N) is coupled to the output node (15), and remaining amplifiers between the first and Nth stages (10.sub.2 to 10.sub.N−1) coupled to successive junctions in the cascade of quarter wavelength transmission lines (11.sub.1 to 11.sub.N−1). The amplifier arrangement is further configured such that apart from first and second amplifiers (10.sub.1 and 10.sub.2) coupled to first and second junctions of the cascade of quarter wavelength transmission lines, the remaining amplifiers (10.sub.3 to 10.sub.N) are coupled to their respective junctions of the cascade of quarter wavelength transmission lines such that successive pairs of amplifiers are either coupled via respective connecting quarter wavelength transmission lines (13) to their respective junctions, or coupled directly to their respective junctions.