An amplifier circuit includes a main amplifier and an auxiliary circuit that improves a slew rate of the main amplifier. The main amplifier is composed of a one-stage CMOS amplifier, amplifies a voltage difference between two input signals, and outputs, from output terminals, an output signal corresponding to the voltage difference of the input signals. The auxiliary circuit controls an auxiliary bias current flowing through the output terminals according to the voltage difference of the input signals, and interrupts the auxiliary bias current at a predetermined timing before completion of settling. Such a scheme enables improvement of a slew rate by the auxiliary circuit and high-speed operation as well as reduction of error due to mismatch between the main amplifier and the auxiliary circuit, thereby yielding high-accuracy output signal output therefrom.

A combining balun includes: a first input side conductive member wound around a first axis on a first surface, which intersects with the first axis, and has a first portion between a second axis and the first axis and through which a first input current flows; a second input side conductive member wound around the second axis on the first surface and has a second portion between the second axis and the first portion and through which a second input current flows; a first output side conductive member wound around the first axis on a second surface, which faces the first surface, and has a third portion which faces the first portion; and a second output side conductive member wound around the second axis on the second surface and has a fourth portion which faces the second portion.

A portable communication device including a processor positioned in a first PCB, a communication circuit; and an antenna module. The antenna module includes a second PCB, an antenna array positioned in the second PCB, wherein the antenna array includes a plurality of antennas, a plurality of PAs, a plurality of LNAs, wherein the plurality of LNAs is greater than the plurality of PAs, a first transmission-reception circuit positioned in the second PCB, and a first reception circuit positioned in the second PCB.

A multi-gain LNA with inductive source degeneration is presented. The inductive source degeneration is provided via a tunable degeneration network that includes an inductor in parallel with one or more switchable shunting networks. Each shunting network includes a shunting capacitor that can selectively be coupled in parallel to the inductor. A capacitance of the shunting capacitor is calculated so that a combined impedance of the inductor and the shunting capacitor at a narrowband frequency of operation is effectively an inductance. The inductance is calculated according to a desired gain of the LNA. According to one aspect, the switchable shunting network includes a resistor in series connection with the shunting capacitor to provide broadband frequency response stability of the tunable degeneration network. According to another aspect, the LNA includes a plurality of selectable branches to further control gain of the LNA.

Certain aspects of the present disclosure provide an amplification system. The amplification system generally includes: a first amplifier having an output coupled to an output of the amplification system; a second amplifier, inputs of the first amplifier and the second amplifier being coupled to an input of the amplification system; an impedance coupled to an output of the second amplifier; and a biasing circuit having a first voltage sense input coupled to the output of the first amplifier, a second voltage sense input coupled to the output of the second amplifier, and an output coupled to a bias input of the first amplifier.

In certain aspects, an apparatus includes a first amplifier having a first output and a second output, and a transformer. The transformer includes a first switchable inductor coupled between the first output and the second output, a first capacitor coupled in parallel with the first switchable inductor, a second switchable inductor magnetically coupled to the first switchable inductor, a second capacitor coupled in parallel with the second switchable inductor, a third switchable inductor magnetically coupled to the first switchable inductor, and a third capacitor coupled in parallel with the third switchable inductor.

Transconductor circuits with programmable tradeoff between bandwidth and flicker noise are disclosed. An example circuit includes an input port, an output port, a plurality of transistors, and a switch arrangement that includes a plurality of switches, configured to change coupling between the input port, the output port, and the transistors to place the transconductor circuit in a first or a second mode of operation. An input capacitance of the transconductor circuit operating in the first mode is larger than when the transconductor circuit is operating in the second mode. In the first mode, having a larger input capacitance results in a decreased flicker noise because the amount of flicker noise is inversely proportional to the input capacitance. In the second mode, having a smaller input capacitance leads to an increased flicker noise but that is acceptable for wide-bandwidth applications because wide-bandwidth signals may be less sensitive to flicker noise.

RF transistor amplifiers include an RF transistor amplifier die having a Group III nitride-based semiconductor layer structure and a plurality of gate terminals, a plurality of drain terminals, and at least one source terminal that are each on an upper surface of the semiconductor layer structure, an interconnect structure on an upper surface of the RF transistor amplifier die, and a coupling element between the RF transistor amplifier die and the interconnect structure that electrically connects the gate terminals, the drain terminals and the source terminal to the interconnect structure.

A digital power amplifier for a signal, the digital power amplifier comprising:

a first activatable amplifier;
a second activatable amplifier; and
an output network,
wherein an output of the first amplifier and an output of the second amplifier are coupled to the output network, and
wherein the amplifiers and/or the output network are configured such that four output levels are obtainable at an output of the output network, and said output levels are configured to optimise a linearity of the digital power amplifier for said signal.

A power amplifier circuit includes a first power amplifier, a balun, a second power amplifier, and a third power amplifier. The second and third power amplifiers each include unit bipolar transistors each including a first terminal electrically connected to a reference potential, a second terminal, and a third terminal that outputs an amplified signal; a common input terminal electrically connected to the second terminals of the transistors and receives an RF signal; a common bias terminal electrically connected to the second terminals of the transistors and receives a bias current; a common output terminal electrically connected to the third terminals of the transistors and outputs the amplified signal; and resistance elements each of which is electrically connected between the common input terminal and the second terminal of a corresponding one of the transistors and cuts a DC component of the bias current.