An amplifier includes a package that includes a carrier amplifier having a carrier amplifier input and output, a peaking amplifier having a peaking amplifier input and output, and corresponding input and output leads. The package includes a first integrated passive device including a first capacitor structure. The first integrated passive device includes a first contact pad coupled to the peaking amplifier output and a second contact pad coupled to the peaking output lead. The package includes a second integrated passive device including a second capacitor structure. The second integrated passive device includes a third contact pad coupled to the carrier amplifier output and a fourth contact pad coupled to the carrier output lead. The amplifier includes input circuitry a combining node configured to combine a carrier output signal and a peaking output signal.

An amplifier circuit configuration capable of processing non-contiguous intra-band carrier aggregate (CA) signals using amplifiers is disclosed herein. In some cases, each of a plurality of amplifiers is an amplifier configured as a cascode (i.e., a two-stage amplifier having two transistors, the first configured as a “common source” input transistor, e.g., input field effect transistor (FET), and the second configured in a “common gate” configuration as a cascode output transistor, (e.g. cascode output FET). In other embodiments, the amplifier may have additional transistors (i.e., more than two stages and/or stacked transistors). The amplifier circuit configuration can be operated in either single mode or split mode. A switchable coupling is placed between the drain of the input FETs of each amplifier within the amplifier circuit configuration. During split mode, the coupling is added to the circuit to allow some of the signal present at the drain of each input FET to be coupled to the drain of the other input FET.

The disclosure relates to an electronic device and a method for wireless communication including a power amplification circuit. According to an embodiment, an electronic device may include: a radio frequency processing module comprising radio frequency circuitry, a first power amplification circuit connected to the radio frequency processing module, a second power amplification circuit connected to the radio frequency processing module and the first power amplification circuit, and a front-end module comprising circuitry connected to the second power amplification circuit and an antenna and configured to transmit a signal, wherein the second power amplification circuit is configured to acquire, from the first power amplification circuit, a first signal obtained by amplifying a signal output from the radio frequency processing module and a second signal by amplifying a signal output from the radio frequency processing module, based on a combination of frequency bands for a first communication scheme and a second communication scheme, and switch at least one of the first signal or the second signal to at least one output port connected to the front-end module, based on a first frequency band of the first signal and a second frequency band of the second signal. Other embodiments are also possible.

Systems and methods of multiport amplifier (MPA) implementation system, including: at least one input matrix, including a plurality of complex modulators, wherein each complex modulator is configured to receive an input channel stream, a summation logic block, configured to sum the complex product of the plurality of complex modulators, and a dual Digital to Analog (DAC) converter, configured to receive summation digital complex output from the summation logic block, a plurality of RF modulators, wherein each RF modulator is configured to receive a dual analog output as baseband I/Q branches from a corresponding DAC converter, and a plurality of amplifiers, wherein each complex amplifier is configured to receive the output of a corresponding RF Modulator for amplification to an output RF matrix.

The present disclosure provides a multiple output low noise amplifier circuit, chip and electronic device. The multiple output low noise amplifier circuit includes: a first processing module for amplifying an input voltage signal and converting it into at least two first current signals; a second processing module for impedance matching at the input terminal of the low noise amplifier circuit, and for amplifying the input voltage signal and converting it into at least two second current signals; a voltage output module, connected to the first processing module and the second processing module, for combining the first current signals and the second current signals and converting them into output voltage signals. The low noise amplifier circuit can convert a single input voltage signal to at least two output voltage signals, and is applicable in RF front ends with multiple output terminals.

The present disclosure provides a Multiple Inputs Multiple Ouputs RF front-end amplifier circuit, chip, and electronic device and a method for configuring signal path. The RF front-end amplifier circuit includes: at least two low-noise amplifying modules, each of which amplifies one voltage signal and converts into one or more intermediate current signals; a voltage output module, connected to each of the low-noise amplifying modules, for combining the intermediate current signal output by the low-noise amplifying module and converting them into one or more output voltage signals. The RF front-end amplifier circuit can be applied to an RF front-end with a Multiple Inputs Multiple Outputs structure.

An amplifier circuit includes an input terminal, an output terminal, an amplifier including a first transistor and a second transistor that are connected in parallel, a first capacitor, and a second capacitor, and an inductor. Each of the first transistor and the second transistor has a gate connected to the input terminal, a source connected to ground, and a drain connected to the output terminal. The inductor is provided between the input terminal and a node of parallel connection of the first transistor and the second transistor on the side of the input terminal. The first capacitor is arranged in a path connecting the node and the gate of the first transistor, the second capacitor is arranged in a path connecting the node and the gate of the second transistor, and the capacitance of the first capacitor differs from the capacitance of the second capacitor.

A package (1) includes first and second input terminals (2,3) which are adjacent to each other, and first and second output terminals (4,5) which are adjacent to each other. A first input matching circuit (6), a first delay circuit (7), a second input matching circuit (8), a first amplifier (9), and a first output matching circuit (10) are sequentially connected between the first input terminal (2) and the first output terminal (4) inside the package (1). A third input matching circuit (11), a second amplifier (12), a second output matching circuit (13), a second delay circuit (14), and a third output matching circuit (15) are sequentially connected between the second input terminal (3) and the second output terminal (5) inside the package (1). First to fourth matching circuits (16-19) are respectively connected to the first input terminal (2), the second input terminal (3), the first output terminal (4) and the second output terminal (5) outside the package (1).

Certain aspects of the present disclosure are generally directed to circuitry and techniques for current sensing. For example, certain aspects provide a circuit for signal amplification including a first amplifier, a second amplifier, and a third amplifier. The circuit also includes a first capacitive element coupled between a first output of the first amplifier and a first input of the third amplifier, a second capacitive element coupled between a second output of the first amplifier and a second input of the third amplifier, a third capacitive element coupled between a first output of the second amplifier and the first input of the third amplifier, and a fourth capacitive element coupled between a second output of the second amplifier and the second input of the third amplifier.

A fast-switching power management circuit operable to prolong battery life is provided. The power management circuit includes a voltage circuit that can generate an output voltage for amplifying an analog signal in a number of time intervals and a pair of hybrid circuits each causing the output voltage to change in any of the time intervals. A control circuit is configured to activate any one of the hybrid circuits during a preceding one of the time intervals to cause the output voltage to change in an immediately succeeding one of the time intervals. By starting the output voltage change earlier in the preceding time interval, it is possible to complete the output voltage change within a switching window in the succeeding time interval while concurrently reducing rush current associated with the output voltage change, thus helping to prolong battery life in a device employing the power management circuit.