A variable-gain power amplifying technique includes generating, with a network of one or more reactive components included in an oscillator, a first oscillating signal, and outputting, via one or more taps included in the network of the reactive components, a second oscillating signal. The second oscillating signal has a magnitude that is proportional to and less than the first oscillating signal. The power amplifying technique further includes selecting one of the first and second oscillating signals to use for generating a power-amplified output signal, and amplifying the selected one of the first and second oscillating signals to generate the power-amplified output signal.

Disclosed is an RF (Radio Frequency) power source having a power supply configured to convert an AC (Alternating Current) voltage at a power supply input to a second voltage at a power supply output, and an RF generator configured to receive the second voltage at an RF generator input and to use the second voltage to produce an output RF signal at an RF generator output. According to an embodiment of the disclosure, the power supply performs the voltage conversion without galvanic isolation between the power supply input and the power supply output, which can increase energy efficiency while reducing complexity and cost as well. Instead, the RF generator is provided with galvanic isolation between the RF generator input and the RF generator output, which can be sufficient for achieving galvanic isolation between the power supply input and the RF generator output for safety reasons.

RF transistor amplifiers are provided that include a submount and an RF transistor amplifier die that is mounted on top of the submount. A multi-layer encapsulation is formed that at least partially covers the RF transistor amplifier die. The multi-layer encapsulation includes a first dielectric layer and a first conductive layer, where the first dielectric layer is between a top surface of the RF transistor amplifier die and the first conductive layer.

A scalable periphery tunable matching power amplifier is presented. Varying power levels can be accommodated by selectively activating or deactivating unit cells of which the scalable periphery tunable matching power amplifier is comprised. Tunable matching allows individual unit cells to see a constant output impedance, reducing need for transforming a low impedance up to a system impedance and attendant power loss. The scalable periphery tunable matching power amplifier can also be tuned for different operating conditions such as different frequencies of operation or different modes.

Front-end for processing 2G signal using 3G/4G paths. In some embodiments, a front-end architecture can include a first amplification path and a second amplification path, with each being configured to amplify a 3G/4G signal, and the first amplification path including a phase shifting circuit. The front-end architecture can further include a splitter configured to receive a 2G signal and split the 2G signal into the first and second amplification paths, and a combiner configured to combine amplified 2G signals from the first and second amplification paths into a common output path. The front-end architecture can further include an impedance transformer implemented along the common output path to provide a desired impedance for the combined 2G signal.

A power amplifier circuit includes lower-stage and upper-stage differential amplifying pairs, a combiner, first and second inductors, and first and second capacitors. First and second signals are input into the lower-stage differential amplifying pair. The upper-stage differential amplifying pair outputs first and second amplified signals. The combiner combines the first and second amplified signals. The lower-stage differential amplifying pair includes first and second transistors. A supply voltage is supplied to the collectors of the first and second transistors. The first and second signals are supplied to the bases of the first and second transistors. The upper-stage differential amplifying pair includes third and fourth transistors. A supply voltage is supplied to the collectors of the third and fourth transistors. The emitters of the third and fourth transistors are grounded via the first and second inductors and are connected to the first and second transistors via the first and second capacitors.

Provided are a power amplifier circuit and a communication device that improve a power handling capability required for a filter while increasing output power. A power amplifier circuit includes: an amplifier unit that amplifies an input signal of a time division duplex scheme and outputs a signal to a signal path and a signal to a signal path; a filter that is provided in the signal path and outputs a signal based on the signal; a filter that is provided in the signal path and outputs a signal based on the signal; and a transformer that is connected to the signal path through the filter and connected to the signal path through the filter and outputs an output signal based on the signal and the signal to a signal path.

Methods and circuital arrangements for turning OFF branches of a multi-branch cascode amplifier are presented. First and second switching arrangements coupled to a branch allow turning OFF the branch while protecting transistors of the branch from a supply voltage that may be greater than a tolerable voltage of the transistors. The first switching arrangement includes a transistor-based switch that is in series connection with the transistors of the branch. The first switching arrangement drops the supply voltage during the OFF state of the branch and provides a conduction path for a current through the branch during the ON state of the branch. A resistor and a shunting switch are coupled to a gate of the transistor-based switch to reduce parasitic coupling effects of the transistor-based switch upon an RF signal coupled to the branch during the ON state and OFF state of the branch.

An aspect of the disclosure relates to a receiver, including: a low noise amplifier (LNA); and an input stage coupled to the LNA, wherein the input stage is configured to provide a first passband for a first signal across at least a portion of a first frequency band and a notch to substantially reject a second signal within the first frequency band or a second frequency band in accordance with a first mode of operation, and a second passband for the second signal across the second frequency band in accordance with a second mode of operation. In the first mode, the input stage includes a parallel L-C resonance frequency and an L-match impedance matching circuit. In the second mode, the input stage includes a modified bridge T-coil impedance matching circuit with substantially no electromagnetic coupling between the inductors of the circuit.

A hybrid class-H/predictive class-G switching amplifier architecture and techniques for amplifying a signal (e.g., an audio signal) using such an architecture. One example method of amplification generally includes delaying an input signal to generate a delayed version of the input signal, amplifying the delayed version of the input signal with an amplifier powered by a boost converter, and selectively controlling the boost converter to operate in at least one of a predictive class-G mode or a class-H mode, based on a magnitude of the input signal.