Exemplary aspects are directed to a power-amplification circuit including multiple in-parallel circuit paths, each including a power amplifier driving an immittance converter. Current from each output of the respective immittance converters is combined for delivery to a load. In a more specific example, a control circuit may be used to modulate, such as by enabling or disabling power delivered from, one or more of the power amplifiers for fast, coarse resetting of the overall power delivered to the load, and/or to modulate one or more of the modulate immittance converters (e.g., via a phase or signal-timing adjustment) to finely tune the resetting of the overall power delivered to the load. Using the control circuit for providing both the coarse adjustment and the fine adjustment, and fast acting precise delivery of overall power delivered to a load may be realized for any of a variety of applications.

A low noise amplifier that includes a first cascode, a second cascode, an input circuit, an output node, a first switch, and a second switch. A source of a first common gate transistor and a drain of a first common source transistor of the first cascode are coupled to a first node of the low noise amplifier. The output node is coupled to a drain of the first common gate transistor, and to a drain of a second common gate transistor of the second cascode, thereby coupling the first cascode and the second cascode to a power supply via a load. The first switch is coupled between a gate of the first common gate transistor and the power supply. The second switch is coupled between the first node and the power supply. The first switch is configured to be open and the second switch is configured to be closed when the low noise amplifier operates at a first operational node. The first switch is configured to be closed and the second switch is configured to be open when the low noise amplifier operates at a second operational node that differs from the first operational mode by at least a gain of the low noise amplifier.

An XTC circuit includes delay circuits, differentiated signal generating circuits, and an amplitude adjusting and adding circuit. A signal Da, which is one aggressor signal, is input to the differentiated signal generating circuit after being delayed by the delay circuit, and the differentiated signal generating circuit generates a differentiated signal having a differentiated waveform of the signal Da. In the amplitude adjusting and adding circuit, the differentiated signal generated by the differentiated signal generating circuit is amplitude-adjusted to become a current signal, and the differentiated signal after the amplitude adjustment is current-added to the signal Db.

Circuits and methods for using in parallel amplification and signal combining are described herein. A circuit uses a digitally controlled multistage cascade combiner, a digital phase and drive signal amplifier controller and a digital combiner controller circuit with N parallel signals with constant amplitudes belonging to an alphabet with M discrete values and discrete phases feeding it. The signals resulting from N power amplifiers (PAs) have also constant amplitudes belonging to an alphabet with N discrete values and discrete phases prior to being fed to the multistage combiner. A digital combiner controller circuit generates digital control information to activate, or deactivate, the outputs of the PAs, where a set of digital control signals generated in digital combiner controller are used to control sets of switches, where the signals can be activated at the combiner's inputs, according to their power and phase values. The digital control information ensures that only in-phase signals are combined in the active combiner stage and any difference among the inputs of the combiners is always minimized. Both digital combiner controller and digital drive signal amplifier controller, share information about the signals not to be fed to the multistage combiner, so that PAs drive signals can also be powered off under these circumstances. In provide high efficiency amplification the signal amplifiers employed before the combining stage may be of switched or current source type.

A radio frequency module includes: a module board that includes a first principal surface and a second principal surface on opposite sides of the module board; a power amplifier; a first circuit component; and a power amplifier (PA) control circuit configured to control the power amplifier. The power amplifier includes: an input terminal; an output terminal; first and second amplifying elements disposed parallel to the input terminal; and an output transformer connected between the output terminal and output terminals of the first and second amplifying elements. The PA control circuit is disposed on the second principal surface, and the first and second amplifying elements are both disposed on the first principal surface.

An amplifier includes amplifier circuits connected in series between a ground and a power supply, each amplifier circuit includes: a transistor; and a first capacitance, one end of which is connected to a drain of the transistor, a first amplifier circuit connected closest to the power supply includes a load connected between the drain of the transistor and the power supply, each of the amplifier circuits except for the first amplifier circuit includes a load connected between the drain of the transistor of an own amplifier circuit and a source of the transistor of an amplifier circuit adjacent to the own amplifier circuit, each of the amplifier circuits except for an amplifier circuit connected farthest from the power supply includes a second capacitance connected between the source of the transistor and the ground, and the second capacitance has a capacitance value larger than a capacitance value of the first capacitance.

An uplink multiple input-multiple output (MIMO) transmitter apparatus includes a transmitter chain that includes a sigma-delta circuit that creates a summed (sigma) signal and a difference (delta) signal from two original signals to be transmitted. These new sigma and delta signals are amplified by power amplifiers to a desired output level before having two signals reconstructed from the amplified sigma and amplified delta signals by a second circuit. These reconstructed signals match the two original signals in content but are at a desired amplified level relative to the two original signals. The reconstructed signals are then transmitted through respective antennas as uplink signals. By employing this uplink MIMO transmitter apparatus, it is possible to use smaller power amplifiers, which may reduce footprint, power consumption, and costs of the uplink MIMO transmitter apparatus.

Spatial power-combining devices with reduced dimensions are disclosed. Spatial power-combining devices are provided that employ a hybrid structure including both a planar splitter/combiner and an antipodal antenna array. Planar splitters may be arranged to divide an input signal while antipodal antenna arrays may be arranged to combine amplified signals. In other applications, the order may be reversed such that antipodal antenna arrays are arranged to divide an input signal while a planar combiner is arranged to combine amplified signals. Advantages of such spatial power-combining devices include reduced size and weight while maintaining suitable performance for operation in desired frequency bands.

A flash analog to digital converter includes double differential comparator circuits and a calibration circuit. Each double differential comparator circuit compares a first input signal with a corresponding voltage in a first set of reference voltages, and compares a second input signal with a corresponding voltage in a second set of reference voltages, in order to generate a corresponding signal in first signals. The calibration circuit outputs a first test signal to be the first input signal and outputs a second test signal to be the second input signal in a test mode, and calibrates a common mode level of each of the first input signal and the second input signal, or calibrates at least one first reference voltage in the first set of reference voltages and at least one second reference voltage in the second set of reference voltages according to a distribution of the first signals.

A digital power amplifier for a signal, the digital power amplifier comprising: a first activatable amplifier; a second activatable amplifier; and an output network, wherein an output of the first amplifier and an output of the second amplifier are coupled to the output network, and wherein the amplifiers and/or the output network are configured such that four output levels are obtainable at an output of the output network, and said output levels are configured to optimise a linearity of the digital power amplifier for said signal.