A Doherty amplifier includes: amplifiers including a main amplifier and an auxiliary amplifier; output circuits for increase in back-off amount including a first output circuit disposed between the main amplifier and an output combination unit provided by the amplifiers, and having a first electric length, and a second output circuit disposed between the auxiliary amplifier and the output combination unit, and having a second electric length; and a frequency characteristic compensation circuit for band broadening disposed electrically in parallel to the first output circuit, for compensating for the frequency characteristics of the impedances in the output circuits.

Embodiments of an apparatus that includes a substrate and an inductor residing in the substrate are disclosed. In one embodiment, the inductor is formed as a conductive path that extends from a first terminal to a second terminal. The conductive path has a shape corresponding to a two-dimensional (2D) lobe laid over a three-dimensional (3D) volume. Since the shape of the conductive path corresponds to the 2D lobe laid over a 3D volume, the magnetic field generated by the inductor has magnetic field lines that are predominately destructive outside the inductor and magnetic field lines that are predominately constructive inside the inductor. In this manner, the inductor can maintain a high quality (Q) factor while being placed close to other components.

A power amplifying circuit includes a first amplifier, a second amplifier, a transformer having a primary winding and a secondary winding, and a capacitor. The first amplifier amplifies a signal which is one of differential signals. The second amplifier amplifies a signal which is the other of the differential signals. The primary winding is connected, at its first end, to the first amplifier, and is connected, at its second end, to the second amplifier. The secondary winding is connected, at its first end, to an unbalanced line through which an unbalanced signal is transmitted, and is connected, at its second end, to the ground. The secondary winding is electromagnetically coupled to the primary winding. The capacitor is connected, at its first end, to the midpoint of the primary winding, and is connected, at its second end, to the ground.

An input buffer circuit includes an input differential amplifier unit, a differential amplifier stage, and a buffer. The input differential amplifier unit has input terminals and at least one output terminal, wherein at least two of the input terminals of the input differential amplifier unit are configured to be capacitively coupled respectively so as to provide at least one pair of signal paths for a first input signal and a second input signal of a differential input signal. The differential amplifier stage, coupled to the input differential amplifier unit, has first and second differential input terminals, and a corresponding output terminal, wherein the first and second differential input terminals are capable of being coupled to the first input signal and the second input signal respectively. The buffer, coupled to the output terminal of the differential amplifier stage, is used for outputting an output single-ended signal.

This application relates to an amplifier selectively operable in first or second modes. The first mode is a BTL mode with first and second output drivers (103p, 103n) both active to generate respective driving signals that vary with an input signal. The second mode is an SE mode, where the first output driver (103p) is active to generate a driving signal at and the output of the second driver (103n) is held constant. A controller (201) selectively controls the mode based on an indication of output signal amplitude. In the first mode, a ratio of magnitude of the two driving signals varies with the indication of output signal amplitude, i.e. the magnitudes of the two driving signals may vary so as to be not equal.

Methods and apparatus for processing a substrate. For example, a processing chamber can include a power source, an amplifier connected to the power source, comprising at least one of a gallium nitride (GaN) transistor or a gallium arsenide (GaAs) transistor, and configured to amplify a power level of an input signal received from the power source to heat a substrate in a process volume, and a cooling plate configured to receive a coolant to cool the amplifier during operation.

A power amplifier circuit includes: a high pass filter that has one end into which a high frequency input signal is inputted; a first amplifier that amplifies the high frequency input signal outputted from the other end of the high pass filter and outputs a high frequency signal obtained through the first amplification; a second amplifier that amplifies the high frequency signal and outputs a high frequency output signal obtained through the second amplification; an automatic transformer that performs impedance matching between the first amplifier and the second amplifier; and an impedance circuit, one end of which is electrically connected with the other end of the high pass filter, the other end of which is electrically connected with an output terminal of a bias circuit outputting bias voltage or bias current to the first amplifier, and that outputs the high frequency input signal to the bias circuit.

A flash analog to digital converter includes double differential comparator circuits and a calibration circuit. Each double differential comparator circuit compares a first input signal with a corresponding voltage in a first set of reference voltages, and compares a second input signal with a corresponding voltage in a second set of reference voltages, in order to generate a corresponding signal in first signals. The calibration circuit outputs a first test signal to be the first input signal and outputs a second test signal to be the second input signal in a test mode, and calibrates a common mode level of each of the first input signal and the second input signal, or calibrates at least one first reference voltage in the first set of reference voltages and at least one second reference voltage in the second set of reference voltages according to a distribution of the first signals.

An exemplary device with differential complex neutralization circuit and device structure are disclosed that can provide substantial device gain boosting over a wide bandwidth (BW) for an amplifier core, e.g., for low noise power amplifier, high frequency amplifier, power amplifier, and the like. The device structure includes neutralization capacitors with designed inductors for the collectors, bases, and capacitor feeding that substantially improve the device gain/stability over a wide bandwidth by absorbing the parasitic inductors of the routings/vias and the capacitors and minimizes the passive loss. At high mm-Wave, neutralization can be realized by overlapping metal traces in device layouts to achieve a device gain of greater than unity gain.

A signal booster is disclosed that includes a first interface port, a second interface port, a third interface port, a downlink signal splitter device, an uplink signal splitter device, a main booster and a front-end booster. The uplink signal splitter device can include a first uplink splitter port configured to direct uplink signals from the second interface port towards the first interface port. The uplink signal splitter device can include a second uplink splitter port configured to direct uplink signals from the third interface port towards the first interface port. The main booster can include a main downlink amplification path and a main uplink amplification path. The front-end booster can include a front-end downlink amplification path and a front-end uplink amplification path.