An amplifier circuit configuration capable of processing non-contiguous intra-band carrier aggregate (CA) signals using amplifiers is disclosed herein. In some cases, each of a plurality of amplifiers is an amplifier configured as a cascode (i.e., a two-stage amplifier having two transistors, the first configured as a “common source” input transistor, e.g., input field effect transistor (FET), and the second configured in a “common gate” configuration as a cascode output transistor, (e.g. cascode output FET). In other embodiments, the amplifier may have additional transistors (i.e., more than two stages and/or stacked transistors). The amplifier circuit configuration can be operated in either single mode or split mode. A switchable coupling is placed between the drain of the input FETs of each amplifier within the amplifier circuit configuration. During split mode, the coupling is added to the circuit to allow some of the signal present at the drain of each input FET to be coupled to the drain of the other input FET.

Technology for a repeater with a trumped amplifier network is disclosed. The repeater can include two or more signal paths corresponding to two or more bands. The repeater can include a first coupler network communicatively coupled to the two or more signal paths. The repeater can include a second coupler network communicatively coupled to an antenna port. The repeater can include two or more amplifier networks between the first coupler network and the second coupler network. A signal received via the first coupler network can be distributed to the two or more amplifier networks for amplification and combined using the second coupler network to produce an amplified output signal.

A signal processing system includes n paths of load modulation modules and a combination module, where then paths of load modulation modules are connected in parallel, an output end of each path of load modulation module is connected to an input end of the combination module, and n is an integer greater than 1; the n paths of load modulation modules include one path of main power amplification module and (n-1) paths of auxiliary power amplification modules, and the auxiliary power amplification modules are turned on when power values of signals received by input ends of the load modulation modules are greater than a first threshold; and the main power amplification module includes two outphasing power amplification units, and each path of auxiliary power amplification module includes two outphasing power amplifier arrays or one digital polar power amplifier array.

A power amplifier and power amplification circuit are described herein. An illustrative power amplifier is disclosed to include an input terminal, a drive amplifier connected to the input terminal, and an impedance modulator having a capacitance that is adjusted inversely and proportionately relative to a signal output by the drive amplifier, wherein the impedance modulator provides a feedback loop between an output of the drive amplifier and the input terminal.

A circuit to modulate the power supply to track input or output voltages provided to or output by a plurality of amplifiers to reduce power dissipation is provided. The circuit may include a peak detection circuit configured to receive a plurality of voltages respectively corresponding to the plurality of amplifiers, and to detect and output information regarding a maximum instantaneous voltage from the received plurality of voltages, and a summing circuit configured to output a sum of the information regarding the maximum instantaneous voltage and an amplifier headroom voltage. A reference voltage may be provided for the supply voltage responsive to the output sum. The circuit may also include a scaling circuit configured to scale the output sum, and the reference voltage may be a scaled reference voltage output by the scaling circuit.

A power amplification circuit includes a first amplifier that amplifies a signal split from an input signal, a second amplifier that amplifies a signal having a different phase from the aforementioned signal, third and fourth amplifiers, and a matching network. The matching network includes a first wiring having a first end connected to an output terminal of the first amplifier and a second end connected to an input terminal of the third amplifier, a second wiring having a first end connected to the input terminal of the third amplifier, and electromagnetically coupled to the first wiring, a third wiring having a first end connected to an output terminal of the second amplifier and a second end connected to an input terminal of the fourth amplifier, and a fourth wiring having a first end connected to the input terminal of the fourth amplifier, and electromagnetically coupled to the third wiring.

A radio-frequency module includes a mounting substrate and first and second power amplifiers. The first and second power amplifiers are each mounted on one main surface of the mounting substrate. The first power amplifier includes a first input terminal and a first outer periphery. The first outer periphery includes a first edge section. The second power amplifier includes a second input terminal and a second outer periphery. The second outer periphery includes a second edge section. The second edge section opposes the first edge section in a first direction. The first input terminal is disposed in the first edge section of the first power amplifier. The second input terminal is disposed in the second edge section of the second power amplifier. The first and second input terminals do not overlap each other in the first direction.

A multi-finger transistor includes unit transistors each including a first terminal electrically connected to a reference potential, a second terminal that receives an RF signal and a bias current, and a third terminal that outputs an amplified signal; a common input terminal electrically connected in parallel to the second terminals of the unit transistors and that receives the RF signal; a common bias terminal electrically connected in parallel to the second terminals of the unit transistors and that receives the bias current; a common output terminal electrically connected in parallel to the third terminals of the unit transistors and that outputs the amplified signal; and first resistance elements each of which is electrically connected between the common input terminal and the second terminal of a corresponding one of the unit transistors and each of which cuts a DC component of the bias current.

A noise filtering circuit including: an amplifier which receives a reference bias through a first input terminal, generates an amplified output voltage and outputs the amplified output voltage through an output terminal, and receives an output voltage generated on the basis of the amplified output voltage through a second input terminal; a resistance component connected between the output terminal of the amplifier and the second input terminal; and a capacitor connected to the resistance component.

A measurement system includes a source unit to provide a source signal to a sample and a voltage source and/or a current source and a memory. The system also includes a measurement unit configured to acquire from the sample an measurement signal that may be responsive to the source signal and a voltage measuring unit, a current measuring unit, and/or a capacitance measuring unit, and a memory. The system also includes a control unit including a digital signal processing unit; a source converter; a measurement converter. The system further includes a synchronization unit configured to synchronize clocks of the digital signal processing unit, the source converter, the measurement converter, the source unit, and the measurement unit; a calibration unit for calibrating aspects of the system including the control unit; and a reference voltage supply configured to supply a common reference voltage for the control unit.