A quadrature clock generator is disclosed. The quadrature clock generator may include a first injection-locked oscillator, a phase interpolator, and a second injection-locked oscillator. The first injection-locked oscillator may generate a first plurality clock signals from a first reference clock signal. The phase interpolator may generate a second reference clock signal from the first plurality of clock signals, and the second injection-locked oscillator may generate a second plurality of clock signals from the second reference clock signal. A first quadrature clock signal may be selected from the first plurality of clock signals and a second quadrature clock signal may be selected from the second plurality of reference clock signals.

A distortion compensation apparatus executes a process including: Performing distortion compensation that compensates in advance for a nonlinear distortion occurring when a transmission signal is amplified by a power amplifier; determining whether power of the transmission signal is smaller than a predetermined threshold; holding a gain relating to the distortion compensation or a result of the distortion compensation when the power of the transmission signal is determined to be smaller than the predetermined threshold; and outputting to the power amplifier, when the power of the transmission signal is determined to be smaller than the predetermined threshold, the result of the distortion compensation, and outputting to the power amplifier, when the power of the transmission signal is determined to be equal to or greater than the predetermined threshold, a result of distortion compensation performed using the held, gain, or the held result of the distortion compensation.

A single-wire peer-to-peer (P2P) bus apparatus is provided. The single-wire P2P bus apparatus includes a first peer device and a second peer device(s) coupled to a single-wire bus that correspond to a first bus access priority and a second bus access priority(s), respectively. Any of the first peer device and the second peer device(s) can contend for access to the single-wire bus by asserting a bus contention indication(s) when the single-wire bus is in a defined bus state. A winner for the single-wire bus may be a peer device having a highest bus access priority among those peer devices asserting the bus contention indication(s). In this regard, any peer device on the single-wire bus can have a chance to initiate communications over the single-wire bus, thus making it possible for the single-wire bus to function based on bidirectional P2P bus architecture capable of supporting more application and/or deployment scenarios.

An envelope stacking power amplifier system reduces current for a given output power level without sacrificing the ability to support large voltage swings at saturation and therefore increases efficiency at the maximum linear operating power and all power levels below that. The system includes a stack/unstack controller including circuitry configured to switch the RF power amplifier system between a stacked mode in which first and second RF amplifiers are coupled in a stacked configuration and an unstacked mode in which the first and second RF amplifiers are coupled in an unstacked configuration in response to one or more mode-control signals, the stacked configuration providing reduced current compared to the unstacked configuration.

A multiple-stage amplifier includes a driver stage transistor characterized by a first power density, and a final stage transistor characterized by a second power density that is larger than the first power density. A first drain bias circuit is coupled to a first drain terminal of the driver stage transistor, and is configured to provide a first drain bias voltage to the first drain terminal. A second drain bias circuit is coupled to a second drain terminal of the final stage transistor, and is configured to provide a second drain bias voltage to the second drain terminal, where the second drain bias voltage equals the first drain bias voltage. An interstage impedance matching circuit is coupled between the first drain terminal and a gate terminal of the final stage transistor. The multiple-stage amplifier may be included in a Doherty power amplifier, a transceiver, and/or a transceiver array.

A test system can use first and different second driver stages to provide test signals to a device under test (DUT). A compound stage can receive signals from the driver stages and provide a voltage output signal to the DUT, such as via a gain circuit. The compound stage can include a buffer circuit configured to provide a first portion of the voltage output signal based on a first output signal from the first driver stage, and the compound stage can include a transimpedance circuit configured to provide a second portion of the voltage output signal based on a second output signal from the second driver stage. In an example, the gain circuit can receive a superposition signal comprising the first and second portions of the voltage output signal and, in response, provide a test signal to the DUT.

An envelope tracking (ET) radio frequency (RF) front-end circuit is provided. The ET RF front-end circuit includes an ET integrated circuit(s) (ETIC(s)), a local transceiver circuit, a target voltage circuit(s), and a number of power amplifiers. The local transceiver circuit receives an input signal(s) from a coupled baseband transceiver and generates a number of RF signals. The target voltage circuit(s) generates a time-variant ET target voltage(s) based on the input signal(s). The ETIC(s) generates multiple ET voltages based on the time-variant ET target voltage(s). The power amplifiers amplify the RF signals based on the ET voltages. Given that the time-variant ET target voltage(s) is generated inside the self-contained ET RF front-end circuit, it is possible to reduce distortion in the time-variant ET target voltage(s), thus helping to improve operating efficiency of the power amplifiers, especially when the RF signals are modulated with a higher modulation bandwidth (e.g., ≥200 MHz).

An amplifier includes amplifier circuits connected in series between a ground and a power supply, each amplifier circuit includes: a transistor; and a first capacitance, one end of which is connected to a drain of the transistor, a first amplifier circuit connected closest to the power supply includes a load connected between the drain of the transistor and the power supply, each of the amplifier circuits except for the first amplifier circuit includes a load connected between the drain of the transistor of an own amplifier circuit and a source of the transistor of an amplifier circuit adjacent to the own amplifier circuit, each of the amplifier circuits except for an amplifier circuit connected farthest from the power supply includes a second capacitance connected between the source of the transistor and the ground, and the second capacitance has a capacitance value larger than a capacitance value of the first capacitance.

An integrated circuit device is provided. In some examples, the integrated circuit device includes a first amplifier path, a second amplifier path coupled in parallel with the first amplifier path, a matching network coupled to the first amplifier path and the second amplifier path, and an antenna coupled to the matching network. In some such examples, the first amplifier path includes a first differential power amplifier coupled to the matching network, and the second amplifier path includes a second differential power amplifier coupled to the matching network. The integrated circuit device may further include a controller coupled to selectively enable the first amplifier path to provide a transmitter output power within a first range and to selectively enable the second amplifier path to provide a transmitter output power within a second range that is different from the first range.

An electronic device including: a modem configured to process a baseband signal; an intermediate frequency (IF) transceiver configured to convert the baseband signal provided from the modem into an IF band signal; and a radio frequency (RF) transceiver configured to convert the IF band signal provided from the IF transceiver into an RF band signal, wherein the RF transceiver includes a power amplifier configured to amplify the RF band signal, and a temperature sensor unit to detect a temperature of the power amplifier, and wherein the modem includes a controller configured to control an input power inputted to the RF transceiver based on the temperature of the power amplifier detected by the temperature sensor unit.