An amplifier circuit includes a primary differential amplifier circuit connected to receive a differential input and provide a primary differential output with a first non-linearity. A secondary differential amplifier circuit is connected to receive the differential input. The secondary differential amplifier circuit is configured to generate a secondary differential output with a second non-linearity. The secondary differential output and the primary differential output are coupled together with opposing polarities such that the second non-linearity cancels out at least the first non-linearity.

Examples disclosed herein relate to a high gain active relay antenna system. The active relay antenna system comprises a first antenna pair having a first receive antenna and a first transmit antenna to communicate wireless signals in a forward link from a base station to a plurality of users; and a second antenna pair having a second receive antenna and a second transmit antenna to communicate wireless signals in a return link from the plurality of users to the base station. The active relay antenna system further comprises a first active relay section and a second active relay section to provide for adjustable power gain in the wireless signals.

A distributed amplifier with low supply voltage and low power consumption is provided. The distributed amplifier includes an input terminal inputting an input signal; an output terminal outputting an output signal; an amplifier unit; a gate line circuit connected to the input terminal, a first load circuit and the amplifier unit; a second load circuit; a drain line circuit connected to the second load circuit, the amplifier unit and the output terminal; and a bias voltage circuit connected between the drain line circuit and the output terminal, wherein the bias voltage circuit includes a voltage source; an inductor connected to the voltage source and a terminal of the drain line circuit; and a capacitor multiplier connected to the inductor, the drain line circuit and the output terminal.

A method and an apparatus are provided for calibrating digital pre-distortion (DPD) of an electronic device. A respective signal is received, by each of a first plurality of receiving antennas, from each of a second plurality of transmitting antennas. A DPD function is determined for each of the second plurality of transmitting antennas based on the received signals. A combined DPD function of the second plurality of transmitting antennas is determined based on the DPD functions and phase shifter settings associated with the second plurality of transmitting antennas.

The inventive concept relates to a communication device comprising a DPD processor configured to output a plurality of pre-distorted signals by pre-distorting each of a plurality of input signals using an extracted feedback signal, a first signal combiner configured to combine a plurality of feedback signals corresponding to the plurality of pre-distorted signals and output a combined feedback signal, an analog-to-digital converter configured to convert the combined feedback signal into a digital signal and output a digital-converted combined feedback signal and a signal extractor configured to extract the digital-converted combined feedback signal and output the extracted feedback signal.

A radio frequency (RF) signal transceiver is provided. The RF signal transceiver includes a first transformer, a signal transceiving processor, a signal receiving amplifier, and a signal transmitting amplifier. The first transformer is coupled to an antenna through a first end of a primary side, and two endpoints of a secondary side of the first transformer receive and transmit a pair of differential signals. The signal transceiving processor receives a pair of input differential signals from the secondary side of the first transformer and generates a pair of processed differential signals. The signal receiving amplifier is coupled to the signal transceiving processor and is configured to receive and amplify the pair of processed differential signals. The signal transmitting amplifier is coupled to the secondary side of the first transformer and provides a pair of transmission differential signals to the secondary side.

A system and method for operating a system including at least one active electronically scanned array (AESA) element incorporates drain voltage amplifier control (DRAVAC) to maintain the power amplifiers of the AESA elements at a constant gain compression level. A processor of the AESA system may dynamically program, monitor, or adjust each individual array element or component thereof. As the RF output power of the power amplifiers varies, constant gain compression is achieved by dynamically adjusting the RF input power and drain voltage to the power amplifiers. An AESA element may incorporate built-in self-test circuitry for detecting faults in the power supply to the power amplifiers as well as calibrating and calculating RF output power for a given input power by controlling the bias of a pass device serving as the amplifier current source.

A power amplifier circuit includes an input-stage power amplifier configured to receive a radio-frequency input signal, an output-stage power amplifier configured to output an amplified radio-frequency output signal, and an intermediate-stage power amplifier disposed between the input-stage power amplifier and the output-stage power amplifier. The intermediate-stage power amplifier includes a first transistor, a second transistor, and a capacitor having a first end connected to an emitter of the first transistor and a second end connected to a collector of the second transistor. The intermediate-stage power amplifier receives a signal at a base of the second transistor thereof and outputs an amplified signal from a collector of the first transistor thereof.

In accordance with an aspect of the present disclosure, there is provided a power amplification apparatus, the apparatus comprising: an input part; a first-1 transformer and a first-2 transformer connected to the input part in parallel; a first amplifier and a second amplifier connected to the first-1 transformer and the first-2 transformer, respectively; a first switch connected to one side of the first-2 transformer; a second-1 transformer and a second-2 transformer connected to the first amplifier and the second amplifier, respectively, and connected to an output part in parallel; and a second switch connected to one side of the second-2 transformer.

A power splitter that amplifies an input radio-frequency (RF) signal. The power splitter uses a single transistor in a common emitter stage of a cascode amplifier and two or more common base stages of the cascode amplifier to amplify and to split the input RF signal. A common base biasing signal can be used to simultaneously enable two or more of the common base stages to generate two or more amplified RF output signals.