A test system can use first and different second driver stages to provide test signals to a device under test (DUT). A compound stage can receive signals from the driver stages and provide a voltage output signal to the DUT, such as via a gain circuit. The compound stage can include a buffer circuit configured to provide a first portion of the voltage output signal based on a first output signal from the first driver stage, and the compound stage can include a transimpedance circuit configured to provide a second portion of the voltage output signal based on a second output signal from the second driver stage. In an example, the gain circuit can receive a superposition signal comprising the first and second portions of the voltage output signal and, in response, provide a test signal to the DUT.

An RF module includes a switch IC having connection electrodes on a first main face and connection electrodes on a second main face; a mounting substrate which has a first mounting face at the first main face side and a second mounting face at the second main face side and in which the switch IC is mounted; signal lines for a band A, which are formed at the first mounting face side of the mounting substrate; signal lines for a band B, which are formed at the second mounting face side of the mounting substrate; a band A filter; and a band B filter. Among the band A filter and the band B filter, only the band A filter is mounted on the first mounting face and only the band B filter is mounted on the second mounting face.

A semiconductor device includes a plurality of unit cell transistors on a common semiconductor structure, the unit cell transistors electrically connected in parallel, and each unit cell transistor including a respective gate finger. Respective threshold voltages of first and second of the unit cell transistors differ by at least 0.1 volts and/or threshold voltages of first and second segments of a third of the unit cell transistors differ by at least 0.1 volts.

A power amplifier module includes first and second amplifiers, a first bias circuit, and an adjusting circuit. The first amplifier amplifies a first signal. The second amplifier amplifies a second signal based on an output signal from the first amplifier. The first bias circuit supplies a bias current to the first amplifier via a current path on the basis of a bias drive signal. The adjusting circuit includes an adjusting transistor having first, second, and third terminals. A first voltage based on a power supply voltage is supplied to the first terminal. A second voltage based on the bias drive signal is supplied to the second terminal. The third terminal is connected to the current path. The adjusting circuit adjusts the bias current on the basis of the power supply voltage supplied to the first amplifier.

A Doherty amplifier includes a divider configured to divide input power into first input power and second input power, and a carrier amplifier configured to amplify the first input power. The Doherty amplifier includes an adaptive attenuator configured to attenuate the second input power, the adaptive attenuator being configured to increase an attenuation amount upon detecting that the second input power is less than a predetermined value. The Doherty amplifier includes a peaking amplifier configured to amplify the attenuated second input power, and a combiner configured to combine output power of the carrier amplifier with output power of the peaking amplifier.

An amplifier device includes a substrate, a composite packaged amplifier having a bottom plate and an output plate, a first amplifier and a second amplifier provided on the bottom plate, a combining node that combines an output of the first amplifier with an output of the second amplifier, an output matching circuits provided on the bottom plate, that has a first transmission line provided between the first amplifier and the combining node, and a second transmission line provided between the combining node and the second amplifier, a third transmission line having one transmission line on which the output plate is mounted and other transmission line that connects the one transmission line to the external port, and wirings connecting to one terminal of the output plate and the combining node. A length of the output plate and the other transmission line is equal or less than π/4 radian for a signal.

A high frequency module includes a transmission power amplifier, a bump electrode connected to the transmission power amplifier, and a mounting board on which the transmission power amplifier is mounted, wherein the mounting board includes a via conductor having an elongated shape in the plan view of the mounting board, a board main part placed outside the via conductor, and an insulating part placed inside the via conductor, and the bump electrode and the via conductor are connected while at least partially overlapping each other in the foregoing plan view, and the board main part and the insulating part are each composed of an insulating material of the same kind.

A power amplifier circuit includes a first amplifier that amplifies an input signal and outputs an output signal; a second amplifier that, in accordance with a control signal, amplifies a signal corresponding to the input signal, generates a signal having an opposite phase to that of the output signal, and adds the signal to the output signal; and a control circuit that supplies the control signal to the second amplifier. The control circuit outputs the control signal so that during operation of the power amplifier circuit in a first power mode, a gain of the second amplifier is not less than zero and less than a predetermined level and during operation in a second power mode lower than the first power mode in output power level, a gain of the second amplifier is not less than the predetermined level and less than a gain of the first amplifier.

Provided is a power amplification module that includes: a first transistor, a first signal being inputted to a base thereof; a second transistor, the first signal being inputted to a base thereof and a collector thereof being connected to a collector of the first transistor; a first resistor, a first bias current being supplied to one end thereof and another end thereof being connected to the base of the first transistor; a second resistor, one end thereof being connected to the one end of the first resistor and another end thereof being connected to the base of the second transistor; and a third resistor, a second bias current being supplied to one end thereof and another end thereof being connected to the base of the second transistor.

Various embodiments of the present technology may provide methods and apparatus for an amplifier integrated circuit. The amplifier integrated circuit may provide two amplifiers, one amplifier set to a low gain bandwidth product to amplify at a higher speed and the other amplifier set to a high gain bandwidth product to amplify at a lower speed. The amplifier integrated circuit may further provide a switching circuit connected to the amplifiers, wherein the switching circuit is responsive to a control signal and operates to selectively activate the high speed amplifier and the low speed amplifier in sequence.