Charge-pump tracker circuitry is disclosed having a first switch network configured to couple a first capacitor between a voltage input terminal and a ground terminal during a first charging phase and couple the first capacitor between the voltage input terminal and a pump output terminal during a first discharging phase. A second switch network is configured to couple the second capacitor between the voltage input terminal and the ground terminal during a second charging phase and couple the second capacitor between the voltage input terminal and the pump output terminal during a second discharging phase. A switch controller is configured to control the first switch network and the second switch network so that the first discharging phase and the second discharging phase are in unison in a parallel mode and so that the first discharging phase and the second discharging phase alternate in an interleaved mode.

A power amplifier module includes a combining circuit including a combiner. The combining circuit further includes a first inductor connected in series between an output terminal of a first amplifier and the combiner, a second inductor connected in series between an output terminal of a second amplifier and the combiner, and a second capacitor having an end connected to the combiner and another end grounded. A phase of a third signal from the output terminal of the first amplifier to the second amplifier through the combiner is delayed by about 45 degrees in the first inductor and the second capacitor, and is delayed by about 45 degrees in the second inductor and the second capacitor. A phase of the third signal from the output terminal of the first amplifier to the second amplifier through the first capacitor is advanced by about 90 degrees.

A method for increasing efficiency of a radio frequency (RF) amplifier employing laterally diffused metal oxide semiconductor (LDMOS) transistors coupled to an RF exciter including determining an emission mode of modulated RF input signals generated by the exciter, if the emission mode is of a type where the modulated RF input signals have a continuously varying envelope, biasing the LDMOS transistors in the RF amplifier for linear operation, and if the emission mode is of a type where the modulated RF input signals do not have a continuously varying envelope, biasing the LDMOS transistors in the RF amplifier with a fixed quiescent drain current and a fixed drain supply voltage for the LDMOS transistors selected to cause the LDMOS transistors to operate in compression.

Disclosed is a method for producing a stage for amplifying the power of a variable envelope signal including at least one amplifier. For each amplifier, a form of ideal variation in average power POUT.sub.L is selected. For each value of each setting parameter and for each average input power value, a value of an optimisation criterion is calculated on the basis of the mathematical expectation of at least one optimisation parameter. An optimum value of each setting parameter is determined and the amplification stage is produced with a number of amplifiers in parallel determined on the basis of an average output power value and with, for each amplifier, matching circuits providing the optimum values of the setting parameters. The invention also relates to an amplification stage produced in this manner.

A power amplifier. The power amplifier includes a plurality of parallel coupled transistors. Each transistor has a control terminal coupled to receive a signal to be amplified and an output terminal coupled to a node. The power amplifier also includes a matching network having an input coupled to the node and an output coupleable to a load. The power amplifier further includes a first circuit branch forming a choke and harmonic trap of the power amplifier. The first circuit branch includes a first inductance, a second inductance and a first capacitor. The first inductance has a first terminal coupled to the node and a second terminal coupled to a first terminal of the second inductance. A second terminal of the second inductance is coupled to AC ground. The first capacitor is coupled in parallel with the second inductance.

A circuit includes a first transistor having a first control input and first and current terminals. The circuit also includes a second transistor having a second control input and third and fourth current terminals. The third current terminal couples to the first current terminal at a first node. An output stage has a first input, a second input, and an output stage output. The first input couples to the fourth current terminal, and the second input couples to the second current terminal. A resistor has first and second resistor terminals. The first resistor terminal couples to the output stage output, and the second resistor terminal couples to the second control input. A third transistor has a third control input, a fifth current terminal, and a sixth current terminal. The fifth current terminal couples to the first resistor terminal, and the sixth current terminal couples to the second resistor terminal.

Systems and methods for communicating electromagnetic signals and/or power and, more particularly for example, to power combiners and similar systems and methods for communicating electromagnetic signals and/or power generated by amplifiers to loads, are described herein. In at least example embodiment, a power amplifier system includes first and second amplifier circuits and a power combiner circuit coupled to each of the first and second amplifier circuits and having a first microstrip transmission line component, a slotline formation, and an additional coupling component that is capable of being at least indirectly coupled to a load, where the first microstrip transmission line component and additional coupling component are electromagnetically coupled by way of the slotline formation.

The present disclosure provides a power amplifier circuit capable of suppressing the occurrence of noises while enabling control of an output power level. The power amplifier circuit includes a first transistor that amplifies a first signal; a bias circuit that supplies a bias current or voltage based on a control signal to the first transistor; a second transistor to which a control current based on the control signal is supplied, which has an emitter or a source thereof connected to a collector or a drain of the first transistor, and from which a second signal obtained by amplifying the first signal is output; and a first feedback circuit provided between the collector or the drain of the second transistor and the base or the gate of the second transistor.

A polar transmitter including a digital power amplifier cell that includes a first circuit and an amplifier circuit. The first circuit is configured to receive a phase modulated carrier signal and to generate a PMOS control signal and an NMOS control signal such that the PMOS control signal and the NMOS control signal have different duty cycles. The amplifier circuit is configured to receive the PMOS control signal at a PMOS transistor and the NMOS control signal at an NMOS transistor. The first circuit is configured to align the PMOS control signal and the NMOS control signal with respect to one another such that a time that the NMOS transistor and the PMOS transistor of the amplifier circuit are simultaneously conducting is minimized. The amplifier circuit is configured to generate an amplified modulated carrier signal in response to the PMOS and NMOS control signals.

An amplifier circuit configuration capable of processing non-contiguous intra-band carrier aggregate (CA) signals using amplifiers is disclosed herein. In some cases, each of a plurality of amplifiers is an amplifier configured as a cascode (i.e., a two-stage amplifier having two transistors, the first configured as a common source input transistor, e.g., input field effect transistor (FET), and the second configured in a common gate configuration as a cascode output transistor, (e.g. cascode output FET). In other embodiments, the amplifier may have additional transistors (i.e., more than two stages and/or stacked transistors). The amplifier circuit configuration can be operated in either single mode or split mode. A switchable coupling is placed between the drain of the input FETs of each amplifier within the amplifier circuit configuration. During split mode, the coupling is added to the circuit to allow some of the signal present at the drain of each input FET to be coupled to the drain of the other input FET.