Circuitry for driving a load, the circuitry comprising: driver circuitry; and load sensing circuitry, wherein the circuitry is operable in: a driving mode of operation in which the driver circuitry supplies a drive signal to a load coupled to the circuitry; and a load sensing mode of operation, for estimating a characteristic of a load coupled to the circuitry based on a signal output by the load sensing circuitry in response to a stimulus signal, wherein the circuitry is configured to, in response to a request for operation of the circuitry in the load sensing mode: compare an indication of a current through the load to a predefined threshold; and if the indication of the current through the load meets the predefined threshold, prevent or delay operation in the load sensing mode.

Integrated circuitry implementing amplifier circuitry, the integrated circuitry comprising first amplifier circuitry and second amplifier circuitry, the first and second amplifier circuitry being configurable as first and second single-ended amplifiers or as a differential amplifier, wherein the first amplifier circuitry comprises: a first input stage; a first half-bridge output stage having an output coupled to a first output terminal of the integrated circuitry; a first feedback path coupling a first input of the first input stage to a first sense terminal of the first amplifier circuitry; a second feedback path coupling a second input of the first input stage to a second sense terminal of the first amplifier circuitry; and a first shunt resistor coupling the output of the first half-bridge output stage to the first feedback path, wherein the second amplifier circuitry comprises: a second input stage; and a second half-bridge output stage having an output coupled to a second output terminal of the integrated circuitry, and wherein the first amplifier circuitry further comprises a second shunt resistor coupling the second feedback path to a dedicated shunt resistor terminal of the integrated circuitry, such that the second shunt resistor is directly accessible from outside the integrated circuitry.

Integrated circuitry implementing amplifier circuitry, the integrated circuitry comprising first amplifier circuitry and second amplifier circuitry, the first and second amplifier circuitry being configurable as first and second single-ended amplifiers or as a differential amplifier, wherein the first amplifier circuitry comprises: a first input stage; a first half-bridge output stage having an output coupled to a first output terminal of the integrated circuitry; a first feedback path coupling a first input of the first input stage to a first sense terminal of the first amplifier circuitry; a second feedback path coupling a second input of the first input stage to a second sense terminal of the first amplifier circuitry; and a first shunt resistor coupling the output of the first half-bridge output stage to the first feedback path, wherein the second amplifier circuitry comprises: a second input stage; and a second half-bridge output stage having an output coupled to a second output terminal of the integrated circuitry, and wherein the first amplifier circuitry further comprises a second shunt resistor coupling the second feedback path to a dedicated shunt resistor terminal of the integrated circuitry, such that the second shunt resistor is directly accessible from outside the integrated circuitry.

A power amplification system comprises a current source configured to provide a bias current, a current mirror configured to mirror the bias current, and a comparator configured to compare the mirrored bias current to a threshold current and, in response to the mirrored bias current exceeding the threshold current, cause a reduction of output power.

A power amplification system comprises a current source configured to provide a bias current, a current mirror configured to mirror the bias current, and a comparator configured to compare the mirrored bias current to a threshold current and, in response to the mirrored bias current exceeding the threshold current, cause a reduction of output power.

A device includes a semiconductor die including a transistor. The transistor includes a plurality of parallel transistor elements. Each transistor element includes a drain region, a source region, and a gate region. The semiconductor die includes a first temperature sensor between a first transistor element in the plurality of transistor elements and a second transistor element in the plurality of transistor elements. The first temperature sensor is configured to generate a first output signal having a magnitude that is proportional to a temperature of the first temperature sensor.

A device includes a semiconductor die including a transistor. The transistor includes a plurality of parallel transistor elements. Each transistor element includes a drain region, a source region, and a gate region. The semiconductor die includes a first temperature sensor between a first transistor element in the plurality of transistor elements and a second transistor element in the plurality of transistor elements. The first temperature sensor is configured to generate a first output signal having a magnitude that is proportional to a temperature of the first temperature sensor.

An RF transmitter (1) having a gate-segmented power output stage (2) and a digital driver (5). The gate-segmented power output stage (2) includes a field-effect transistor with a plurality of gate fingers (32) and drain fingers (31) that define a gate periphery. The field-effect transistor comprises a plurality of power output stage segments (3) that each correspond to a respective part of the gate periphery, and that each have a respective power output stage segment input (4). The digital driver (5) has control outputs (6) which are connected to corresponding ones of the respective power output stage segment inputs (4), and is configured for individually switching each of the power output stage segments (3) between an on mode and a cut-off mode in dependence of one or more input signals to obtain a modulated RF carrier signal at an output (7) of the gate-segmented power output stage (2).

A power amplifier circuit includes amplifying transistors electrically cascade-connected, amplifying a signal supplied to a base, and outputting an amplified signal; a first resistive element having end parts connected to the base of a first amplifying transistor; a second resistive element having end parts connected to the base of a second amplifying transistor, which is an amplifying transistor located closer to an input side than the first amplifying transistor; a first bias supplying transistor having an emitter connected to one of the end parts of the first resistive element; a second bias supplying transistor having an emitter connected to one of the end parts of the second resistive element; and a bias current compensation transistor having a base connected to the end part of the first resistive element, a collector connected to the end part of the second resistive element, and an emitter connected to ground.

A power amplifier circuit includes amplifying transistors electrically cascade-connected, amplifying a signal supplied to a base, and outputting an amplified signal; a first resistive element having end parts connected to the base of a first amplifying transistor; a second resistive element having end parts connected to the base of a second amplifying transistor, which is an amplifying transistor located closer to an input side than the first amplifying transistor; a first bias supplying transistor having an emitter connected to one of the end parts of the first resistive element; a second bias supplying transistor having an emitter connected to one of the end parts of the second resistive element; and a bias current compensation transistor having a base connected to the end part of the first resistive element, a collector connected to the end part of the second resistive element, and an emitter connected to ground.