A semiconductor device includes a semiconductor substrate and first and second bipolar transistors. The semiconductor substrate includes first and second main surfaces opposing each other. The first bipolar transistor is formed on the first main surface of the semiconductor substrate and includes a first emitter layer. The second bipolar transistor is formed on the first main surface of the semiconductor substrate and includes a second emitter layer and a resistor layer. The resistor layer is stacked on the second emitter layer in a direction normal to the first main surface.

A semiconductor device includes a semiconductor substrate and first and second bipolar transistors. The semiconductor substrate includes first and second main surfaces opposing each other. The first bipolar transistor is formed on the first main surface of the semiconductor substrate and includes a first emitter layer. The second bipolar transistor is formed on the first main surface of the semiconductor substrate and includes a second emitter layer and a resistor layer. The resistor layer is stacked on the second emitter layer in a direction normal to the first main surface.

An amplifier having a Radio Frequency (RF) power level detector circuit for producing a control signal in accordance with a power level of an RF input signal. The control signal indicates whether the power level of the input signal is within a predetermined range of power levels greater than zero. A bias circuit is fed by the control signal, for producing a fixed bias voltage at a gate electrode of a field effect transistor (FET) to establish a predetermined quiescent current for the FET when the control signal indicates the power level of the RF input signal is within the predetermined range of power levels and to reduce the bias voltage to reduce the predetermined quiescent current when the control signal indicates the power level of the RF input signal is below the predetermined range of power levels.

An amplifier having a Radio Frequency (RF) power level detector circuit for producing a control signal in accordance with a power level of an RF input signal. The control signal indicates whether the power level of the input signal is within a predetermined range of power levels greater than zero. A bias circuit is fed by the control signal, for producing a fixed bias voltage at a gate electrode of a field effect transistor (FET) to establish a predetermined quiescent current for the FET when the control signal indicates the power level of the RF input signal is within the predetermined range of power levels and to reduce the bias voltage to reduce the predetermined quiescent current when the control signal indicates the power level of the RF input signal is below the predetermined range of power levels.

Amplifier configuration for load-line enhancement is described herein. In some implementations, an apparatus includes an amplifier. The amplifier includes at least one plus transistor stack, at least one minus transistor stack, and at least one inductor. The at least one plus transistor stack is coupled to a plus amplifier node and a plus input node. The at least one minus transistor stack is coupled to a minus amplifier node and a minus input node. The at least one inductor is coupled between the plus amplifier node and the minus amplifier node, with the at least one inductor including an inter-inductor node. The amplifier also includes a minus power switch coupled between the minus amplifier node and one or more supply voltages and an inductor power switch coupled between the inter-inductor node and at least one supply voltage.

Amplifier configuration for load-line enhancement is described herein. In some implementations, an apparatus includes an amplifier. The amplifier includes at least one plus transistor stack, at least one minus transistor stack, and at least one inductor. The at least one plus transistor stack is coupled to a plus amplifier node and a plus input node. The at least one minus transistor stack is coupled to a minus amplifier node and a minus input node. The at least one inductor is coupled between the plus amplifier node and the minus amplifier node, with the at least one inductor including an inter-inductor node. The amplifier also includes a minus power switch coupled between the minus amplifier node and one or more supply voltages and an inductor power switch coupled between the inter-inductor node and at least one supply voltage.

A power amplifier includes a carrier amplifier that operates from when an input signal is small, a peak amplifier that starts to operate when the input signal becomes large, a phase adjusting circuit that adjusts phases of an output of the carrier amplifier and an output of the peak amplifier, an impedance transforming line that transforms a load of the carrier amplifier when the input signal is small, and has a characteristic impedance close to an optimum load impedance of the carrier amplifier, and a circuit that is arranged between the output of the carrier amplifier and the impedance transforming line and reduces an output capacitance of the carrier amplifier.

A power amplifier includes a carrier amplifier that operates from when an input signal is small, a peak amplifier that starts to operate when the input signal becomes large, a phase adjusting circuit that adjusts phases of an output of the carrier amplifier and an output of the peak amplifier, an impedance transforming line that transforms a load of the carrier amplifier when the input signal is small, and has a characteristic impedance close to an optimum load impedance of the carrier amplifier, and a circuit that is arranged between the output of the carrier amplifier and the impedance transforming line and reduces an output capacitance of the carrier amplifier.

Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are presented, where the amplifier can have a varying supply voltage that varies according to a control voltage. The control voltage can be related to a desired output power of the amplifier and/or to an envelope signal of an input signal to the amplifier. Particular biasing for selectively controlling the stacked transistors to operate in either a saturation region or a triode region is also presented. Benefits of such controlling, including increased linear response of an output power of the amplifier, are also discussed.

Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are presented, where the amplifier can have a varying supply voltage that varies according to a control voltage. The control voltage can be related to a desired output power of the amplifier and/or to an envelope signal of an input signal to the amplifier. Particular biasing for selectively controlling the stacked transistors to operate in either a saturation region or a triode region is also presented. Benefits of such controlling, including increased linear response of an output power of the amplifier, are also discussed.