Spatial power-combining devices and antenna assemblies for spatial power-combining devices are disclosed. The disclosure relates to spatial power-combining devices with segmented waveguides and antennas. The spatial power-combining devices may be designed for high efficiency, high or low frequency ranges, ultra-wide bandwidth operation, and high output power. A spatial power-combining device may include a plurality of amplifiers, an output center waveguide including an output inner housing and an output outer housing, and an output coaxial waveguide. The output center waveguide may form a plurality of output center waveguide segments that are discontinuous with each other. Each output center waveguide segment may include a different portion of the output inner housing and the output outer housing. An antenna for a spatial power-combining device may include a plurality of antenna segments, each of which includes a different portion of a signal conductor and a ground conductor of the antenna.

A power amplification module includes first and second amplifiers for first and second communication modes, a bypass line that bypasses the first or second amplifier, an input switch circuit that supplies a radio frequency signal to the first or second amplifier in accordance with a communication mode when a desired output level is equal to or greater than a reference level, and that supplies a radio frequency signal to the bypass line when the desired output level is less than the reference level, and an output switch circuit that outputs a first amplified signal from the first amplifier or a second amplified signal from the second amplifier in accordance with the communication mode when the desired output level is equal to or greater than the reference level, and that outputs a radio frequency signal output from the bypass line when the desired output level is less than the reference level.

A power amplification module includes first and second amplifiers for first and second communication modes, a bypass line that bypasses the first or second amplifier, an input switch circuit that supplies a radio frequency signal to the first or second amplifier in accordance with a communication mode when a desired output level is equal to or greater than a reference level, and that supplies a radio frequency signal to the bypass line when the desired output level is less than the reference level, and an output switch circuit that outputs a first amplified signal from the first amplifier or a second amplified signal from the second amplifier in accordance with the communication mode when the desired output level is equal to or greater than the reference level, and that outputs a radio frequency signal output from the bypass line when the desired output level is less than the reference level.

A flip chip circuit comprising: a semiconductor substrate; a power amplifier provided on the semiconductor substrate; and a metal pad configured to receive an electrically conductive bump for connecting the flip chip to external circuitry. At least a portion of the power amplifier is positioned directly between the metal pad and the semiconductor substrate.

A flip chip circuit comprising: a semiconductor substrate; a power amplifier provided on the semiconductor substrate; and a metal pad configured to receive an electrically conductive bump for connecting the flip chip to external circuitry. At least a portion of the power amplifier is positioned directly between the metal pad and the semiconductor substrate.

Embodiments described herein relate to a Doherty amplifier. The Doherty amplifier may include a main amplifier and a first peak amplifier, a second peak amplifier, and a third peak amplifier, each amplifier having an input and an output. The Doherty amplifier may also include a combining network configured for combining signals emerging at outputs of the amplifiers. The signals are combined at a combining node. The combining network includes a first impedance inverter arranged in between the output of the main amplifier and the output of the third peak amplifier. The combining network also includes a second impedance inverter arranged in between the output of the first peak amplifier and the output of the second peak amplifier. The combining network also includes a first 180 degrees phase shifter and a second 180 degrees phase shifter. Additionally, the combining network includes a third impedance inverter.

Embodiments described herein relate to a Doherty amplifier. The Doherty amplifier may include a main amplifier and a first peak amplifier, a second peak amplifier, and a third peak amplifier, each amplifier having an input and an output. The Doherty amplifier may also include a combining network configured for combining signals emerging at outputs of the amplifiers. The signals are combined at a combining node. The combining network includes a first impedance inverter arranged in between the output of the main amplifier and the output of the third peak amplifier. The combining network also includes a second impedance inverter arranged in between the output of the first peak amplifier and the output of the second peak amplifier. The combining network also includes a first 180 degrees phase shifter and a second 180 degrees phase shifter. Additionally, the combining network includes a third impedance inverter.

Envelope tracking can be employed to reduce power consumption of a power amplifier, but envelope tracking can introduce nonlinearities to a power amplifier. These nonlinearities can manifest themselves as noise at the output of the power amplifier. Embodiments described herein provide techniques for characterizing a parameter indicative of power amplifier noise when envelope tracking is employed. Measurement of this parameter can permit power amplifier designers to decide whether to forgo envelope tracking if a power amplifier is too susceptible to such noise, redesign the power amplifier to improve compatibility with envelope tracking, or to employ distortion compensation circuitry to reduce the noise output by the power amplifier. Counterintuitively, this distortion compensation circuitry may involve increasing the power, such as the envelope tracking power supply. However, increasing the power may be a desirable trade-off for increased linearity.

Envelope tracking can be employed to reduce power consumption of a power amplifier, but envelope tracking can introduce nonlinearities to a power amplifier. These nonlinearities can manifest themselves as noise at the output of the power amplifier. Embodiments described herein provide techniques for characterizing a parameter indicative of power amplifier noise when envelope tracking is employed. Measurement of this parameter can permit power amplifier designers to decide whether to forgo envelope tracking if a power amplifier is too susceptible to such noise, redesign the power amplifier to improve compatibility with envelope tracking, or to employ distortion compensation circuitry to reduce the noise output by the power amplifier. Counterintuitively, this distortion compensation circuitry may involve increasing the power, such as the envelope tracking power supply. However, increasing the power may be a desirable trade-off for increased linearity.

Electronic circuits with a switch and methods for operating a switch in an electronic circuit. A first amplifier is coupled by a first path with an antenna. A second amplifier is coupled by a second path with the antenna. A transistor is coupled with the first path at a node. The first transistor includes a back gate. A back-gate bias circuit is coupled with the back gate of the first transistor. The back-gate bias circuit is configured to supply a bias voltage to the back gate of the first transistor that lowers a threshold voltage of the transistor.