Embodiments disclosed herein generally relate to power amplifier matching circuits used for matching impedance and harmonic control in a device, such as a cellular phone. In one example, a power amplifier matching circuit includes two DVCs, four inductors, a transistor, and a capacitor. Utilizing the two DVCs, the impedance matching ratio and the center frequency of the circuit are capable of adjustment as needed. Moreover, the inclusion of the two DVCs may also prevent harmonic frequencies from undesirably passing through the power amplifier matching circuit to the antenna of a cellular device. The power amplifier matching circuit may be used in conjunction with an amplifier, where the output of the amplifier is proportional to the current in the circuit.

Apparatus and methods for an improved-efficiency Doherty amplifier are described. The Doherty amplifier may include a two-stage peaking amplifier that transitions from an “off” state to an “on” state later and more rapidly than a single-stage peaking amplifier used in a conventional Doherty amplifier. The improved Doherty amplifier may operate at higher gain values than a conventional Doherty amplifier, with no appreciable reduction in signal bandwidth.

An integrated circuit architecture and circuitry is defined by a die structure with a plurality of exposed conductive pads arranged in a grid of rows and columns. The die structure has a first operating frequency region with a first transmit and receive chain, and a second operating frequency region with a second transmit chain and a second receive chain. There is a shared region of the die structure defined by an overlapping segment of the first operating frequency region and the second operating frequency region with a shared power supply input conductive pad connected to the first transmit chain, the second transmit chain, the first receive chain, and the second receive chain, and a shared power detection output conductive pad connected to the first transmit chain and the second transmit chain.

An integrated circuit architecture and circuitry is defined by a die structure with a plurality of exposed conductive pads arranged in a grid of rows and columns. The die structure has a first operating frequency region with a first transmit and receive chain, and a second operating frequency region with a second transmit chain and a second receive chain. There is a shared region of the die structure defined by an overlapping segment of the first operating frequency region and the second operating frequency region with a shared power supply input conductive pad connected to the first transmit chain, the second transmit chain, the first receive chain, and the second receive chain, and a shared power detection output conductive pad connected to the first transmit chain and the second transmit chain.

A power amplifier circuit includes a first transistor, a capacitor, and a second transistor. The first transistor has an emitter electrically connected to a reference potential, a base, and a collector electrically connected to a first power supply potential. A first end of the capacitor is electrically connected to the collector of the first transistor. The second transistor has an emitter electrically connected to a second end of the capacitor and electrically connected to the reference potential, a base, and a collector electrically connected to the first power supply potential. An RF output signal obtained by amplifying the RF input signal is output from the collector of the second transistor. A second bias circuit includes a third transistor having a collector electrically connected to a second power supply potential, a base, and an emitter from which the second bias current or voltage is output.

A power amplifier circuit includes a first transistor, a capacitor, and a second transistor. The first transistor has an emitter electrically connected to a reference potential, a base, and a collector electrically connected to a first power supply potential. A first end of the capacitor is electrically connected to the collector of the first transistor. The second transistor has an emitter electrically connected to a second end of the capacitor and electrically connected to the reference potential, a base, and a collector electrically connected to the first power supply potential. An RF output signal obtained by amplifying the RF input signal is output from the collector of the second transistor. A second bias circuit includes a third transistor having a collector electrically connected to a second power supply potential, a base, and an emitter from which the second bias current or voltage is output.

Circuitry, which includes a package interface, a radio frequency (RF) amplification circuit, and a closed-loop gain linearization circuit. The package interface receives an RF signal and provides an amplified RF signal. The RF amplification circuit amplifies the RF signal in accordance with a gain of the RF amplification circuit so as to generate the amplified RF signal. In one embodiment, the closed-loop gain linearization circuit is configured to endogenously establish a target gain magnitude using the RF signal and linearize the gain of the RF amplification circuit in accordance with the target gain magnitude. By endogenously establishing the target gain magnitude using the RF signal, the closed-loop gain linearization circuit can provide linearity with greater independence from external control circuitry.

Circuitry, which includes a package interface, a radio frequency (RF) amplification circuit, and a closed-loop gain linearization circuit. The package interface receives an RF signal and provides an amplified RF signal. The RF amplification circuit amplifies the RF signal in accordance with a gain of the RF amplification circuit so as to generate the amplified RF signal. In one embodiment, the closed-loop gain linearization circuit is configured to endogenously establish a target gain magnitude using the RF signal and linearize the gain of the RF amplification circuit in accordance with the target gain magnitude. By endogenously establishing the target gain magnitude using the RF signal, the closed-loop gain linearization circuit can provide linearity with greater independence from external control circuitry.

Apparatus and methods for an inverted Doherty amplifier operating at gigahertz frequencies are described. RF fractional bandwidth and signal bandwidth may be increased over a conventional Doherty amplifier configuration when impedance-matching components and an impedance inverter in an output network of the inverted Doherty amplifier are designed based on characteristics of the main and peaking amplifier and asymmetry factor of the amplifier.

Antenna waveguide transitions for solid state power amplifiers (SSPAs) are disclosed. An SSPA includes a waveguide channel that is configured to propagate an input signal, such as an electromagnetic signal, from an input port to a solid state amplifier for amplification. The waveguide channel is further configured to propagate an amplified signal from the solid state amplifier to an output port. Waveguide transitions to and from the solid state amplifier are bandwidth matched to the waveguide channel. Additionally, the waveguide transitions may be thermally coupled to the waveguide channel. The waveguide transitions may include antenna structures that have a signal conductor and a ground conductor. In this manner, the SSPA may have improved broadband coupling as well as improved thermal dissipation for heat generated by the solid state amplifier.