An embodiment of a Doherty amplifier module includes a substrate, an RF signal splitter, a carrier amplifier die, and a peaking amplifier die. The RF signal splitter divides an input RF signal into first and second input RF signals, and conveys the first and second input RF signals to first and second splitter output terminals. The carrier amplifier die includes one or more first power transistors configured to amplify, along a carrier signal path, the first input RF signal to produce an amplified first RF signal. The peaking amplifier die includes one or more second power transistors configured to amplify, along a peaking signal path, the second input RF signal to produce an amplified second RF signal. The carrier and peaking amplifier die are coupled to the substrate so that the RF signal paths through the carrier and peaking amplifier die extend in substantially different (e.g., orthogonal) directions.

An embodiment of a Doherty amplifier module includes a substrate, an RF signal splitter, a carrier amplifier die, and a peaking amplifier die. The RF signal splitter divides an input RF signal into first and second input RF signals, and conveys the first and second input RF signals to first and second splitter output terminals. The carrier amplifier die includes one or more first power transistors configured to amplify, along a carrier signal path, the first input RF signal to produce an amplified first RF signal. The peaking amplifier die includes one or more second power transistors configured to amplify, along a peaking signal path, the second input RF signal to produce an amplified second RF signal. The carrier and peaking amplifier die are coupled to the substrate so that the RF signal paths through the carrier and peaking amplifier die extend in substantially different (e.g., orthogonal) directions.

An amplifier circuit is disclosed suitable for feeding a loudspeaker system having plural drivers. The amplifier circuit has an output stage and plural output connectors such that there is an output connector for each driver, wherein the output stage is connected separately to each output connector for independent connection to each driver. A method of feeding a loudspeaker system having plural drivers with an amplifier circuit having an output stage is also disclosed.

An amplifier circuit is disclosed suitable for feeding a loudspeaker system having plural drivers. The amplifier circuit has an output stage and plural output connectors such that there is an output connector for each driver, wherein the output stage is connected separately to each output connector for independent connection to each driver. A method of feeding a loudspeaker system having plural drivers with an amplifier circuit having an output stage is also disclosed.

A low-noise amplifier is disclosed. The amplifier includes a signal amplifier having an amplifier signal output, a first filter capacitor, a buffer amplifier having a buffer amplifier input and a buffer amplifier output; and a switching network. The first filter capacitor has first and second terminals. The second terminal is connected to a power rail. The amplifier signal output is connected to the buffer amplifier input by a first direct current path and the buffer amplifier output to the first terminal of the first filter capacitor by a second direct current path during a first time period. The amplifier signal output is connected directly to the first terminal of the first filter capacitor by a third direct current path during a second time period, and the amplifier signal output to the first terminal of the first filter capacitor through a resistor during a third time period.

A system for offset cancellation for driving a display panel includes: a plurality of source amplifiers driving the display panel; an image analyzer configured to receive a data input of an image frame and analyze the data input; and a chopping pattern controller connected with the image analyzer and configured to determine a chopping pattern that fits the data input based on analysis results of the image analyzer, and apply the determined chopping pattern to the source amplifiers. The source amplifiers are divided into N groups while the chopping pattern controller is configured to drive source amplifiers in each group by a single chopping control signal. The image analyzer is configured to generate an indicator that indicates whether image data being analyzed corresponds to a general image or one of pre-registered killer pattern images. A method for offset cancellation for driving a display panel is also provided.

A chip module, including a radio frequency integrated circuit (RFIC) chip and a package, and a method and system for designing the module. Chip and package design are performed so the RF front end (FE) is split between chip and package. The chip includes an amplifier with a first differential port and the package includes a passive device and matching network with a second differential port connected to the first differential port. The second differential port is power matched to the first differential port using complex power matching based on port voltage reflection coefficients in order to achieve improved performance (i.e., a peak power transfer across a bandwidth as opposed to at only one frequency). The power matching process can result in a chip power requirement reduction that allows for device size scaling. Thus, designing the chip and designing the package is iteratively repeated in a chip-package co-optimization process.

A chip module, including a radio frequency integrated circuit (RFIC) chip and a package, and a method and system for designing the module. Chip and package design are performed so the RF front end (FE) is split between chip and package. The chip includes an amplifier with a first differential port and the package includes a passive device and matching network with a second differential port connected to the first differential port. The second differential port is power matched to the first differential port using complex power matching based on port voltage reflection coefficients in order to achieve improved performance (i.e., a peak power transfer across a bandwidth as opposed to at only one frequency). The power matching process can result in a chip power requirement reduction that allows for device size scaling. Thus, designing the chip and designing the package is iteratively repeated in a chip-package co-optimization process.

A portable communication device including a processor positioned in a first PCB, a communication circuit; and an antenna module. The antenna module includes a second PCB, an antenna array positioned in the second PCB, wherein the antenna array includes a plurality of antennas, a plurality of PAs, a plurality of LNAs, wherein the plurality of LNAs is greater than the plurality of PAs, a first transmission-reception circuit positioned in the second PCB, and a first reception circuit positioned in the second PCB.

A portable communication device including a processor positioned in a first PCB, a communication circuit; and an antenna module. The antenna module includes a second PCB, an antenna array positioned in the second PCB, wherein the antenna array includes a plurality of antennas, a plurality of PAs, a plurality of LNAs, wherein the plurality of LNAs is greater than the plurality of PAs, a first transmission-reception circuit positioned in the second PCB, and a first reception circuit positioned in the second PCB.