H03F3/213

Compact RFIC with stacked inductor and capacitor
11522506 · 2022-12-06 · ·

Various embodiments relate to an integrated circuit including a transistor device having input and output terminals, and an inductor-capacitor (LC) circuit coupled to one of the terminals of the transistor device. The LC circuit includes a capacitor having a top plate and a bottom plate, a inductor having a coil structure, and a connector configured to couple the inductor and an interior portion the top plate of the capacitor. The inductor at least partially overlaps the capacitor.

SYMMETRIC LAYOUT FOR HIGH-VOLTAGE AMPLIFIER

A packaged semiconductor die may include a package terminal array comprising a plurality of terminals, wherein a spacing between the plurality of terminals of the ball grid array is less than 0.5 mm. First and second high-voltage circuits of the die may output a differential signal to a first and second terminal that may exceed 15 volts, in which the first high-voltage circuit and the second high-voltage circuit are positioned symmetrically around an axis and in which the first terminal and the second terminal are located at an edge of the package terminal array. A low-voltage circuit may be coupled to a third terminal and positioned between the first high-voltage circuit and the second high-voltage circuit, wherein the low-voltage circuit comprises circuitry organized in columns aligned along an axis and having a width defined by a fraction of the terminal spacing pitch.

Direct substrate to solder bump connection for thermal management in flip chip amplifiers

Solder bumps are placed in direct contact with the silicon substrate of an amplifier integrated circuit having a flip chip configuration. A plurality of amplifier transistor arrays generate waste heat that promotes thermal run away of the amplifier if not directed out of the integrated circuit. The waste heat flows through the thermally conductive silicon substrate and out the solder bump to a heat-sinking plane of an interposer connected to the amplifier integrated circuit via the solder bumps.

Direct substrate to solder bump connection for thermal management in flip chip amplifiers

Solder bumps are placed in direct contact with the silicon substrate of an amplifier integrated circuit having a flip chip configuration. A plurality of amplifier transistor arrays generate waste heat that promotes thermal run away of the amplifier if not directed out of the integrated circuit. The waste heat flows through the thermally conductive silicon substrate and out the solder bump to a heat-sinking plane of an interposer connected to the amplifier integrated circuit via the solder bumps.

Radio frequency (RF) integrated circuit performing signal amplification operation to support carrier aggregation and receiver including the same

A receiver includes an amplification block supporting carrier aggregation (CA). The amplification block includes a first amplifier circuit configured to receive a radio frequency (RF) input signal at a block node from an outside source, amplify the RF input signal, and output the amplified RF input signal as a first RF output signal. The first amplifier circuit includes a first amplifier configured to receive the RF input signal through a first input node to amplify the RF input signal, and a first feedback circuit coupled between the first input node and a first internal amplification node of the first amplifier to provide feedback to the first amplifier.

Radio frequency (RF) integrated circuit performing signal amplification operation to support carrier aggregation and receiver including the same

A receiver includes an amplification block supporting carrier aggregation (CA). The amplification block includes a first amplifier circuit configured to receive a radio frequency (RF) input signal at a block node from an outside source, amplify the RF input signal, and output the amplified RF input signal as a first RF output signal. The first amplifier circuit includes a first amplifier configured to receive the RF input signal through a first input node to amplify the RF input signal, and a first feedback circuit coupled between the first input node and a first internal amplification node of the first amplifier to provide feedback to the first amplifier.

Generator
11516946 · 2022-11-29 · ·

Provided is a generator that includes a housing, a high-power circuit including a power amplifier, and a low-power circuit. An air flow guidance plate divides the housing into at least two compartments including a high-power compartment and a low-power compartment. The high-power circuit is disposed within the high-power compartment and the low-power circuit is disposed within the low-power compartment.

Generator
11516946 · 2022-11-29 · ·

Provided is a generator that includes a housing, a high-power circuit including a power amplifier, and a low-power circuit. An air flow guidance plate divides the housing into at least two compartments including a high-power compartment and a low-power compartment. The high-power circuit is disposed within the high-power compartment and the low-power circuit is disposed within the low-power compartment.

HIGH ELECTRON MOBILITY TRANSISTORS HAVING IMPROVED PERFORMANCE
20220376099 · 2022-11-24 ·

A GaN-based high electron mobility transistor (HEMT) device includes a semiconductor structure comprising a channel layer and a barrier layer sequentially stacked on a substrate, a drain contact and a source contact on the barrier layer, and a gate contact on the barrier layer between the drain contact and the source contact. A sheet resistance of a drain access region and/or a source access region of the semiconductor structure is between 300 and 400 Ω/sq.

HIGH ELECTRON MOBILITY TRANSISTORS HAVING IMPROVED PERFORMANCE
20220376099 · 2022-11-24 ·

A GaN-based high electron mobility transistor (HEMT) device includes a semiconductor structure comprising a channel layer and a barrier layer sequentially stacked on a substrate, a drain contact and a source contact on the barrier layer, and a gate contact on the barrier layer between the drain contact and the source contact. A sheet resistance of a drain access region and/or a source access region of the semiconductor structure is between 300 and 400 Ω/sq.