A Radio Frequency (RF) circuit including a receive path, a transmit path, a switching circuit, and an output configured to receive RF signals from an antenna in a receive mode of operation, and to provide RF signals to the antenna in a transmit mode of operation. The receive path is configured to be coupled between a low-noise amplifier and the output. The switching circuit is located in the receive path and is configured, in the receive mode, to selectively couple the low-noise amplifier to the output and to pass the received RF signals from the output to the low-noise amplifier. The transmit path is configured to be coupled between a power amplifier and the output, to provide, in the transmit mode, signals from the power amplifier to the output, bypassing the switching circuit, and to have, in receive mode of operation, an off-state impedance of at least 200+j*13 Ohm.

A Radio Frequency (RF) circuit including a receive path, a transmit path, a switching circuit, and an output configured to receive RF signals from an antenna in a receive mode of operation, and to provide RF signals to the antenna in a transmit mode of operation. The receive path is configured to be coupled between a low-noise amplifier and the output. The switching circuit is located in the receive path and is configured, in the receive mode, to selectively couple the low-noise amplifier to the output and to pass the received RF signals from the output to the low-noise amplifier. The transmit path is configured to be coupled between a power amplifier and the output, to provide, in the transmit mode, signals from the power amplifier to the output, bypassing the switching circuit, and to have, in receive mode of operation, an off-state impedance of at least 200+j*13 Ohm.

A multiple-path amplifier (e.g., a Doherty amplifier) includes a first transistor (e.g., a main amplifier FET), a second transistor (e.g., a peaking amplifier FET), a combining node, and a shunt-inductance circuit. The first and second amplifiers and the combining node structure are integrally-formed with a semiconductor die, and the shunt-inductance circuit is integrated with the die. Outputs of the first and second transistors are electrically coupled to the combining node structure. The shunt-inductance circuit is electrically coupled between the combining node structure and a ground reference node. The shunt-inductance circuit includes a shunt inductance (e.g., including wirebond(s) and/or spiral inductor(s)) that is integrated with the semiconductor die. The multiple-path amplifier also may include an integrated phase shifter/impedance inverter coupled between the outputs of the first and second transistors, and which is configured to impart a 90-degree phase delay between intrinsic drains of the first and second transistors.

A multiple-path amplifier (e.g., a Doherty amplifier) includes a first transistor (e.g., a main amplifier FET), a second transistor (e.g., a peaking amplifier FET), a combining node, and a shunt-inductance circuit. The first and second amplifiers and the combining node structure are integrally-formed with a semiconductor die, and the shunt-inductance circuit is integrated with the die. Outputs of the first and second transistors are electrically coupled to the combining node structure. The shunt-inductance circuit is electrically coupled between the combining node structure and a ground reference node. The shunt-inductance circuit includes a shunt inductance (e.g., including wirebond(s) and/or spiral inductor(s)) that is integrated with the semiconductor die. The multiple-path amplifier also may include an integrated phase shifter/impedance inverter coupled between the outputs of the first and second transistors, and which is configured to impart a 90-degree phase delay between intrinsic drains of the first and second transistors.

Examples disclosed herein relate to a high gain active relay antenna system. The active relay antenna system comprises a first antenna pair having a first receive antenna and a first transmit antenna to communicate wireless signals in a forward link from a base station to a plurality of users; and a second antenna pair having a second receive antenna and a second transmit antenna to communicate wireless signals in a return link from the plurality of users to the base station. The active relay antenna system further comprises a first active relay section and a second active relay section to provide for adjustable power gain in the wireless signals.

Examples disclosed herein relate to a high gain active relay antenna system. The active relay antenna system comprises a first antenna pair having a first receive antenna and a first transmit antenna to communicate wireless signals in a forward link from a base station to a plurality of users; and a second antenna pair having a second receive antenna and a second transmit antenna to communicate wireless signals in a return link from the plurality of users to the base station. The active relay antenna system further comprises a first active relay section and a second active relay section to provide for adjustable power gain in the wireless signals.

In integrating RF power amplifier circuits on a package, at least one bias voltage is coupled to at least one amplifier circuit on the package via two or more pins/connectors. In particular, at least one of a gate and drain bias voltage is coupled to one or more amplifier circuits via at least two pins/connectors. In some embodiments, the two or more bias voltage pins/connectors are connected together on the package, placing the pins/connectors in parallel, which reduces an inductance associated with the pins/connectors. In some embodiments, at least of the two pins/connectors connected to the same bias voltage are disposed on either side of an RF signal pin/conductor, simplifying the routing of signals on the package, affording greater flexibility of placement and routing on the package.

In integrating RF power amplifier circuits on a package, at least one bias voltage is coupled to at least one amplifier circuit on the package via two or more pins/connectors. In particular, at least one of a gate and drain bias voltage is coupled to one or more amplifier circuits via at least two pins/connectors. In some embodiments, the two or more bias voltage pins/connectors are connected together on the package, placing the pins/connectors in parallel, which reduces an inductance associated with the pins/connectors. In some embodiments, at least of the two pins/connectors connected to the same bias voltage are disposed on either side of an RF signal pin/conductor, simplifying the routing of signals on the package, affording greater flexibility of placement and routing on the package.

An envelope tracking (ET) integrated circuit (IC) (ETIC) is provided. The ETIC is configured to generate an ET voltage based on a supply voltage(s) and provide the ET voltage to an amplifier circuit(s) for amplifying a radio frequency (RF) signal(s). Notably, the RF signal(s) may be modulated in different modulation bandwidths and the amplifier circuit(s) may correspond to different load-line impedances. Accordingly, the ETIC may need to adapt the ET voltage such that the ETIC and the amplifier circuit(s) can operate at higher efficiencies. In examples discussed herein, the ETIC is configured to determine a time-variant peak of the ET voltage and adjust the supply voltage(s) accordingly. As a result, it may be possible to improve operating efficiency of the ETIC in face of a wide range of bandwidth and/or load-line requirements.

An envelope tracking (ET) integrated circuit (IC) (ETIC) is provided. The ETIC is configured to generate an ET voltage based on a supply voltage(s) and provide the ET voltage to an amplifier circuit(s) for amplifying a radio frequency (RF) signal(s). Notably, the RF signal(s) may be modulated in different modulation bandwidths and the amplifier circuit(s) may correspond to different load-line impedances. Accordingly, the ETIC may need to adapt the ET voltage such that the ETIC and the amplifier circuit(s) can operate at higher efficiencies. In examples discussed herein, the ETIC is configured to determine a time-variant peak of the ET voltage and adjust the supply voltage(s) accordingly. As a result, it may be possible to improve operating efficiency of the ETIC in face of a wide range of bandwidth and/or load-line requirements.