In a transistor formed on a semiconductor die mounted on a substrate, where the transistor output is connected to a circuit on the substrate, a bond pad electrically connected to a transistor drain finger manifold extends less than the full length of the manifold. By controlling the length of the bond pad, the parasitic capacitance it contributes may be controlled. In applications such as a Doherty amplifier, this parasitic capacitance forms part of the quarter-wave transmission line of an impedance inverter, and hence directly impacts amplifier performance. In particular, by reducing the parasitic capacitance contribution from transistor output bond pads, the bandwidth of a Doherty amplifier circuit may be improved. At GHz frequencies and with state of the art transistor device feature sizes, concerns about phase mismatch between drain finger outputs are largely moot.

A power amplifier (20) for a transmitter circuit (10) is disclosed. The power amplifier (20) comprises at least one field-effect transistor (100, 100n, 100p) having a gate terminal (110, 110n, 110p) and a bulk terminal (120, 120n, 120p), wherein the at least one field-effect transistor (100, 100n, 100n) is configured to receive an input voltage at the gate terminal (110, 110p, 110n) and a dynamic bias voltage at the bulk terminal (120, 120n, 120p). Furthermore, the power amplifier (20) comprises a bias-voltage generation circuit (130). The input voltage is a linear function of an input signal. The bias-voltage generation circuit (130) is configured to generate the dynamic bias voltage as a nonlinear function of an envelope of the input signal.

A power amplifier (20) for a transmitter circuit (10) is disclosed. The power amplifier (20) comprises at least one field-effect transistor (100, 100n, 100p) having a gate terminal (110, 110n, 110p) and a bulk terminal (120, 120n, 120p), wherein the at least one field-effect transistor (100, 100n, 100n) is configured to receive an input voltage at the gate terminal (110, 110p, 110n) and a dynamic bias voltage at the bulk terminal (120, 120n, 120p). Furthermore, the power amplifier (20) comprises a bias-voltage generation circuit (130). The input voltage is a linear function of an input signal. The bias-voltage generation circuit (130) is configured to generate the dynamic bias voltage as a nonlinear function of an envelope of the input signal.

A power amplification module includes first and second amplifiers for first and second communication modes, a bypass line that bypasses the first or second amplifier, an input switch circuit that supplies a radio frequency signal to the first or second amplifier in accordance with a communication mode when a desired output level is equal to or greater than a reference level, and that supplies a radio frequency signal to the bypass line when the desired output level is less than the reference level, and an output switch circuit that outputs a first amplified signal from the first amplifier or a second amplified signal from the second amplifier in accordance with the communication mode when the desired output level is equal to or greater than the reference level, and that outputs a radio frequency signal output from the bypass line when the desired output level is less than the reference level.

A power amplification module includes first and second amplifiers for first and second communication modes, a bypass line that bypasses the first or second amplifier, an input switch circuit that supplies a radio frequency signal to the first or second amplifier in accordance with a communication mode when a desired output level is equal to or greater than a reference level, and that supplies a radio frequency signal to the bypass line when the desired output level is less than the reference level, and an output switch circuit that outputs a first amplified signal from the first amplifier or a second amplified signal from the second amplifier in accordance with the communication mode when the desired output level is equal to or greater than the reference level, and that outputs a radio frequency signal output from the bypass line when the desired output level is less than the reference level.

A power amplifier module includes a substrate including, in an upper surface of the substrate, an active region and an element isolation region. The power amplifier module further includes a collector layer, a base layer, and an emitter layer that are stacked on the active region; an interlayer insulating film that covers the collector layer, the base layer, and the emitter layer; a pad that is thermally coupled to the element isolation region; and an emitter bump that is disposed on the interlayer insulating film, electrically connected to the emitter layer through a via hole provided in the interlayer insulating film, and electrically connected to the pad. In plan view, the emitter bump partially overlaps an emitter region which is a region of the emitter layer and through which an emitter current flows.

A power amplifier module includes a substrate including, in an upper surface of the substrate, an active region and an element isolation region. The power amplifier module further includes a collector layer, a base layer, and an emitter layer that are stacked on the active region; an interlayer insulating film that covers the collector layer, the base layer, and the emitter layer; a pad that is thermally coupled to the element isolation region; and an emitter bump that is disposed on the interlayer insulating film, electrically connected to the emitter layer through a via hole provided in the interlayer insulating film, and electrically connected to the pad. In plan view, the emitter bump partially overlaps an emitter region which is a region of the emitter layer and through which an emitter current flows.

A packaged semiconductor chip includes a power amplifier die including a semiconductor substrate, and an input contact pad, an output contact pad, first and second direct-current (DC) contact pads, one or more transistors having an input coupled to the input contact pad, and an input bias coupling path electrically coupling the first DC contact pad to the second DC contact pad and the input contact pad implemented on the semiconductor substrate. The chip further includes a lead frame having one or more radio-frequency input pins electrically coupled to the input contact pad, one or more radio-frequency output pins electrically coupled to the output contact pad, and first and second input bias pins electrically coupled to the first and second DC contact pads, respectively.

A packaged semiconductor chip includes a power amplifier die including a semiconductor substrate, and an input contact pad, an output contact pad, first and second direct-current (DC) contact pads, one or more transistors having an input coupled to the input contact pad, and an input bias coupling path electrically coupling the first DC contact pad to the second DC contact pad and the input contact pad implemented on the semiconductor substrate. The chip further includes a lead frame having one or more radio-frequency input pins electrically coupled to the input contact pad, one or more radio-frequency output pins electrically coupled to the output contact pad, and first and second input bias pins electrically coupled to the first and second DC contact pads, respectively.

In integrating RF power amplifier circuits on a package, at least one bias voltage is coupled to at least one amplifier circuit on the package via two or more pins/connectors. In particular, at least one of a gate and drain bias voltage is coupled to one or more amplifier circuits via at least two pins/connectors. In some embodiments, the two or more bias voltage pins/connectors are connected together on the package, placing the pins/connectors in parallel, which reduces an inductance associated with the pins/connectors. In some embodiments, at least of the two pins/connectors connected to the same bias voltage are disposed on either side of an RF signal pin/conductor, simplifying the routing of signals on the package, affording greater flexibility of placement and routing on the package.