A power amplifying apparatus includes a first bias circuit configured to generate a first bias current, a first amplification circuit, configured to receive the first bias current, amplify a signal input to the first amplification circuit through a first node, and output a first amplified signal to a second node, a second bias circuit, configured to generate a second bias current which has a magnitude different from a magnitude of the first bias current, and a second amplification circuit, connected in parallel with the first amplification, configured to receive the second bias current, amplify the signal input through the first node, and output a second amplified signal to the second node. The second amplification circuit is configured to output the second amplified signal with a third-harmonic component that has a phase offsetting a third-order intermodulation distortion (IM3) component included in the first amplified signal, based on the second bias current.

A semiconductor apparatus includes the following elements. A substrate includes a ground portion to which a ground potential is supplied. A semiconductor chip is mounted on the substrate and includes first and second output terminals, a first terminator, and a ground terminal. First and second amplifiers are respectively formed in first and second regions of the semiconductor chip and respectively amplify first and second input signals of first and second frequency bands and output first and second amplified signals from the first and second output terminals via first and second output wires. A first harmonic termination circuit includes a first wire which electrically connects the first terminator and the ground portion. A ground wire is disposed between the first wire and the second output wire in a plan view of a main surface of the semiconductor chip and electrically connects the ground terminal and the ground portion.

A semiconductor apparatus includes the following elements. A substrate includes a ground portion to which a ground potential is supplied. A semiconductor chip is mounted on the substrate and includes first and second output terminals, a first terminator, and a ground terminal. First and second amplifiers are respectively formed in first and second regions of the semiconductor chip and respectively amplify first and second input signals of first and second frequency bands and output first and second amplified signals from the first and second output terminals via first and second output wires. A first harmonic termination circuit includes a first wire which electrically connects the first terminator and the ground portion. A ground wire is disposed between the first wire and the second output wire in a plan view of a main surface of the semiconductor chip and electrically connects the ground terminal and the ground portion.

A radio frequency (RF) amplifier circuit includes a field effect transistor (FET) (e.g., a FET belonging to a III-V FET enhancement group), where the FET includes a gate terminal coupled to an RF input node. The circuit further includes a prematch and biasing network coupled between a bias voltage node and the RF input node. The prematch and biasing network includes a nonlinear gate current blocking device configured to block a current from flowing between the bias voltage node and the RF input node.

A radio frequency (RF) amplifier circuit includes a field effect transistor (FET) (e.g., a FET belonging to a III-V FET enhancement group), where the FET includes a gate terminal coupled to an RF input node. The circuit further includes a prematch and biasing network coupled between a bias voltage node and the RF input node. The prematch and biasing network includes a nonlinear gate current blocking device configured to block a current from flowing between the bias voltage node and the RF input node.

A packaged amplifier circuit includes an RF package with a die pad, and RF input and output leads extending away from the die pad opposite directions. An RF transistor die is mounted on the die pad such that a first outer edge side of the RF transistor die faces the first RF lead and a second outer edge side of the RF transistor die faces the second RF lead. A passive electrical connector is integrally formed in the RF transistor die. The passive electrical connector includes a first end connection point closer to the first outer edge side, and a second end connection point closer to the second outer edge side. A first discrete reactive device is mounted on the die pad between the first outer edge side and the first RF lead. The passive electrical connector electrically couples the first discrete reactive device to the second RF lead.

A packaged amplifier circuit includes an RF package with a die pad, and RF input and output leads extending away from the die pad opposite directions. An RF transistor die is mounted on the die pad such that a first outer edge side of the RF transistor die faces the first RF lead and a second outer edge side of the RF transistor die faces the second RF lead. A passive electrical connector is integrally formed in the RF transistor die. The passive electrical connector includes a first end connection point closer to the first outer edge side, and a second end connection point closer to the second outer edge side. A first discrete reactive device is mounted on the die pad between the first outer edge side and the first RF lead. The passive electrical connector electrically couples the first discrete reactive device to the second RF lead.

The present invention provides a class-G amplifier, wherein the class-G amplifier includes an amplifier stage, an impedance detector and a power source. In the operations of the class-G amplifier, the amplifier stage is supplied by a supply voltage, and amplifies an input audio signal to generate an output audio signal, and the impedance detector is configured to detect an output impedance of the amplifier stage to generate a detection result, and the power source refers to the detection result to determine a level and a switching frequency of the supply voltage.

The present invention provides a class-G amplifier, wherein the class-G amplifier includes an amplifier stage, an impedance detector and a power source. In the operations of the class-G amplifier, the amplifier stage is supplied by a supply voltage, and amplifies an input audio signal to generate an output audio signal, and the impedance detector is configured to detect an output impedance of the amplifier stage to generate a detection result, and the power source refers to the detection result to determine a level and a switching frequency of the supply voltage.

Voltage stabilizing and voltage regulating circuits implemented in GaN HEMT technology provide stable output voltages suitable for use in applications such as GaN power transistor gate drivers and low voltage auxiliary power supplies for GaN integrated circuits. Gate driver and voltage regulator modules include at least one GaN D-mode HEMT (DHEMT) and at least two GaN E-mode HEMTs (EHEMTs) connected together in series, so that the at least one DHEMT operates as a variable resistor and the at least two EHEMTs operate as a Zener diode that limits the output voltage. The gate driver and voltage regulator modules may be implemented as a GaN integrated circuits, and may be monolithically integrated together with other components such as amplifiers and power HEMTs on a single die to provide a GaN HEMT power module IC.