Voltage stabilizing and voltage regulating circuits implemented in GaN HEMT technology provide stable output voltages suitable for use in applications such as GaN power transistor gate drivers and low voltage auxiliary power supplies for GaN integrated circuits. Gate driver and voltage regulator modules include at least one GaN D-mode HEMT (DHEMT) and at least two GaN E-mode HEMTs (EHEMTs) connected together in series, so that the at least one DHEMT operates as a variable resistor and the at least two EHEMTs operate as a Zener diode that limits the output voltage. The gate driver and voltage regulator modules may be implemented as a GaN integrated circuits, and may be monolithically integrated together with other components such as amplifiers and power HEMTs on a single die to provide a GaN HEMT power module IC.

A multiple-path amplifier (e.g., a Doherty amplifier) includes a semiconductor die, a radio frequency (RF) signal input terminal, a combining node structure integrally formed with the semiconductor die, and first and second amplifiers (e.g., main and peaking amplifiers) integrally formed with the die. Inputs of the first and second amplifiers are electrically coupled to the RF signal input terminal. A plurality of wirebonds is connected between an output of the first amplifier and the combining node structure. An output of the second amplifier is electrically coupled to the combining node structure (e.g., through a conductive path with a negligible phase delay). A phase delay between the outputs of the first and second amplifiers is substantially equal to 90 degrees. The second amplifier may be divided into two amplifier portions that are physically located on opposite sides of the first amplifier.

A multiple-path amplifier (e.g., a Doherty amplifier) includes a semiconductor die, a radio frequency (RF) signal input terminal, a combining node structure integrally formed with the semiconductor die, and first and second amplifiers (e.g., main and peaking amplifiers) integrally formed with the die. Inputs of the first and second amplifiers are electrically coupled to the RF signal input terminal. A plurality of wirebonds is connected between an output of the first amplifier and the combining node structure. An output of the second amplifier is electrically coupled to the combining node structure (e.g., through a conductive path with a negligible phase delay). A phase delay between the outputs of the first and second amplifiers is substantially equal to 90 degrees. The second amplifier may be divided into two amplifier portions that are physically located on opposite sides of the first amplifier.

A power amplifier includes a semiconductor die, and an amplifier and bias circuit integrally formed with the semiconductor die. The die has opposed first and second sides, and a device bisection line extends between the first and second sides. The bias circuit includes a multi-point input terminal with first and second terminals that are electrically connected through a conductive path that extends across the device bisection line, and one or more bias circuit components connected between the multi-point input terminal and the amplifier. The amplifier may include a field effect transistor (FET) with gate and drain terminals, and the bias circuit component(s) are electrically connected between the multi-point input terminal and the gate terminal. In addition or alternatively, the bias circuit component(s) are electrically connected between a multi-point input terminal and the drain terminal. The one or more components may include a resistor-divider circuit.

A power amplifier includes a semiconductor die, and an amplifier and bias circuit integrally formed with the semiconductor die. The die has opposed first and second sides, and a device bisection line extends between the first and second sides. The bias circuit includes a multi-point input terminal with first and second terminals that are electrically connected through a conductive path that extends across the device bisection line, and one or more bias circuit components connected between the multi-point input terminal and the amplifier. The amplifier may include a field effect transistor (FET) with gate and drain terminals, and the bias circuit component(s) are electrically connected between the multi-point input terminal and the gate terminal. In addition or alternatively, the bias circuit component(s) are electrically connected between a multi-point input terminal and the drain terminal. The one or more components may include a resistor-divider circuit.

A display driver includes an operational amplifier, a D/A conversion circuit, a resistance circuit, and a resistance element. The D/A conversion circuit includes first and second variable resistance circuits including one end to which first and second voltages are input and another end connected to an inverting input node. The resistance circuit is provided between the inverting input node and an output node. The resistor is provided between the output node and the inverting input node. A resistance value of the first variable resistance circuit is set based on upper bit data of display data. A resistance value of the second variable resistance circuit is set based on lower bit data of the display data.

Antenna structures for spatial power-combining devices are disclosed. A spatial power-combining device includes a plurality of amplifier assemblies, and each amplifier assembly includes an amplifier coupled between an input antenna and an output antenna. At least one of the input antenna or the output antenna comprises a nonlinear shape that is configured to propagate a signal along a nonlinear path to or from the amplifier with reduced signal loss. Accordingly, each amplifier may be configured on a corresponding amplifier assembly in a position such that each amplifier is spaced farther apart from other amplifiers in the spatial power-combining device. In this manner, heat generated by the amplifiers may be more evenly dissipated by the spatial power-combining device.

Antenna structures for spatial power-combining devices are disclosed. A spatial power-combining device includes a plurality of amplifier assemblies, and each amplifier assembly includes an amplifier coupled between an input antenna and an output antenna. At least one of the input antenna or the output antenna comprises a nonlinear shape that is configured to propagate a signal along a nonlinear path to or from the amplifier with reduced signal loss. Accordingly, each amplifier may be configured on a corresponding amplifier assembly in a position such that each amplifier is spaced farther apart from other amplifiers in the spatial power-combining device. In this manner, heat generated by the amplifiers may be more evenly dissipated by the spatial power-combining device.

A power amplifier circuit includes a first transistor having a base to which a radio frequency (RF) signal is supplied and a collector to which a variable power-supply voltage corresponding to a level of the RF signal is supplied, and being configured to amplify the RF signal; a bias circuit including a second transistor configured to supply a bias current to the base of the first transistor; and an adjustment circuit configured to cause the bias current to be supplied to the base of the first transistor to decrease with decrease in the variable power-supply voltage by causing a current to be supplied to a base of the second transistor to decrease.

A power amplifier circuit includes a first transistor having a base to which a radio frequency (RF) signal is supplied and a collector to which a variable power-supply voltage corresponding to a level of the RF signal is supplied, and being configured to amplify the RF signal; a bias circuit including a second transistor configured to supply a bias current to the base of the first transistor; and an adjustment circuit configured to cause the bias current to be supplied to the base of the first transistor to decrease with decrease in the variable power-supply voltage by causing a current to be supplied to a base of the second transistor to decrease.