A switch circuit provides a first output signal and a second output signal for switching between ternary modulation and quaternary modulation for a target device. A first output signal is provided from one of a first signal, a second signal and a ground signal according to an input signal and a duty signal, wherein the first signal is generated through performing a one-bit left-shift operation for the input signal, and the second signal is generated through adding the input signal and the duty signal. A second output signal is provided from one of a third signal, a fourth signal and the ground signal according to the input signal and the duty signal, wherein the third signal is generated through subtracting the input signal from the duty signal, and the fourth signal is generated through performing a two's-complement transformation and the one-bit left-shift operation for the input signal.

An amplifier having one or more channels where each channel includes a two half bridges (a master and slave sub-channel). The sub-channels can be connected either in parallel or in a full-bridge configuration via internal switches that route signals to a pair of speaker jacks. One switch in the amplifier has a first position that selectively connects the outputs of the master and slave sub-channel to the same input of the speaker load so that the two sub-channels will drive the speaker load in parallel and a second position where the output of the slave sub-channel is connected to another input of the speaker load so that the master sub-channel and the slave sub-channel will drive the speaker load in a Full-bridge configuration. A second switch has a first position that connects a second input of the speaker load to ground or reference potential of the sub-channels when the speaker load is to be driven in parallel and a second position that is a No-connect position that is used when the speaker load is driven in the Full-bridge configuration and a ground potential is not to be connected to the speaker.

The present invention discloses an audio processing circuit, wherein when the audio processing circuit determines that a signal being processed is a small signal, an output stage uses a regulated supply voltage provided by a voltage regulator, and the output stage uses an open-loop structure to reduce noise of an output audio signal; and when the audio processing circuit determines that the signal being processed is a large signal, the output stage directly uses the supply voltage without using the regulated supply voltage, and the output stage uses a closed-loop structure to reduce the total harmonic distortion of the output audio signal. By using the present invention, the audio processing circuit can have a good performance indicator with a small chip area design.

An amplifier system may include at least one input source, a converter configured to provide voltage rails to an amplifier, the voltage rails including a first voltage rail and a second voltage rail, a MOSFET arranged at a secondary side of the system at the first voltage rail, a second MOSFET arranged at the first voltage rail, a third MOSFET arranged at the second voltage rail, a fourth MOSFET arranged at the second voltage rail; and, a first capacitor arranged at the first voltage rail and a second capacitor arranged at the second voltage rail, the first and forth MOSFETS are configured to operate simultaneously with one another and the second and third MOSFETs are configured to operate simultaneously with one another and opposite of the first and fourth MOSFETs so as to allow synchronous rectification so that the first and second capacitors reciprocally and mutually exclusively charge and discharge.

A full-bridge class-D amplifier circuit comprises first through fourth power devices. First conduction terminals of the first and third power devices are coupled to a first power supply voltage, and second conduction terminals of the second and fourth power devices are coupled to a second power supply voltage. A second conduction terminal of the first power device and a first conduction terminal of the second power device are coupled to a first amplifier output. A second conduction terminal of the third power device and a first conduction terminal of the fourth power device are coupled to a second amplifier output. Left and right driver devices respectively disposed adjacent to left and right sides of the first power device have outputs respectively coupled to left and right control terminals respectively disposed on the left and right sides of the first power device.

A full-bridge class-D amplifier circuit comprises first through fourth power devices. First conduction terminals of the first and third power devices are coupled to a first power supply voltage, and second conduction terminals of the second and fourth power devices are coupled to a second power supply voltage. A second conduction terminal of the first power device and a first conduction terminal of the second power device are coupled to a first amplifier output. A second conduction terminal of the third power device and a first conduction terminal of the fourth power device are coupled to a second amplifier output. Left and right driver devices respectively disposed adjacent to left and right sides of the first power device have outputs respectively coupled to left and right control terminals respectively disposed on the left and right sides of the first power device.

An electronic apparatus is described. The apparatus includes a circuit element configured to output a signal comprising a modulated frequency component. The apparatus also includes a filter arrangement comprising first, second and third notch filter arrangements, wherein each of the first and second notch filter arrangements comprise a first series inductor, and a series shunt configuration comprising a second inductor and a capacitor coupled in series and the third notch filter arrangement comprises a series inductor and a shunt capacitor, wherein each of the notch filter arrangements are configured to generate a notch in a frequency response to attenuate the output signal at a frequency of the modulated frequency component.

An electronic apparatus is described. The apparatus includes a circuit element configured to output a signal comprising a modulated frequency component. The apparatus also includes a filter arrangement comprising first, second and third notch filter arrangements, wherein each of the first and second notch filter arrangements comprise a first series inductor, and a series shunt configuration comprising a second inductor and a capacitor coupled in series and the third notch filter arrangement comprises a series inductor and a shunt capacitor, wherein each of the notch filter arrangements are configured to generate a notch in a frequency response to attenuate the output signal at a frequency of the modulated frequency component.

An amplifier comprises: an input stage, a pulse width modulation stage, and a switched output stage. During operation, the input stage receives an input signal (such as an audio signal). The input stage adjusts the input signal based on feedback from the switched output stage of the amplifier. According to one configuration, the feedback from the switched output stage is a voltage across a flying capacitor disposed in the switched output stage. The pulse width modulation stage uses the adjusted input signal or signals to produce respective pulse width modulation signals that are subsequently used to drive (control) switches in the switched output stage. The switches in the switched output stage generate an output voltage to drive a load based on states of the pulse width modulation signals. Adjustments applied to the input signal based on the feedback maintains the magnitude of the flying capacitor voltage at a desired setpoint.