A load independent inverter comprises a switched mode zero-voltage switching (ZVS) amplifier. The switched mode ZVS amplifier comprising: a pair of circuits comprises: at least a transistor and at least a capacitor arranged in parallel; and at least an inductor arranged in series with the transistor and capacitor. The amplifier further comprises only one ZVS inductor connected to the pair of circuits; and at least a pair of capacitors connected to the ZVS inductor and arranged in series with at least an inductor and at least a resistor.

A first system includes first and second buck-boost amplifiers. The first amplifier is connected to a battery, includes a first inductor and a first plurality of switches connected to the first inductor, and drives first and second loads. The second amplifier is connected to the battery, includes a second inductor and a second plurality of switches connected to the second inductor, and drives the first and second loads. A controller drives the first and second plurality of switches to operate each of the first and second amplifiers in a single inductor multiple output mode. A second system includes multiple buck-boost amplifiers connected to a battery and driving respective loads. Each amplifier includes inductors and switches connected to the inductors. A controller drives the switches to utilize one or more inductors based on an amount of power used by each amplifier to drive the respective loads.

This application relates to an amplifier selectively operable in first or second modes. The first mode is a BTL mode with first and second output drivers (103p, 103n) both active to generate respective driving signals that vary with an input signal. The second mode is an SE mode, where the first output driver (103p) is active to generate a driving signal at and the output of the second driver (103n) is held constant. A controller (201) selectively controls the mode based on an indication of output signal amplitude. In the first mode, a ratio of magnitude of the two driving signals varies with the indication of output signal amplitude, i.e. the magnitudes of the two driving signals may vary so as to be not equal.

A matchless plasma source is described. The matchless plasma source includes a controller that is coupled to a direct current (DC) voltage source of an agile DC rail to control a shape of an amplified square waveform that is generated at an output of a half-bridge transistor circuit. The matchless plasma source further includes the half-bridge transistor circuit used to generate the amplified square waveform to power an electrode, such as an antenna, of a plasma chamber. The matchless plasma source also includes a reactive circuit between the half-bridge transistor circuit and the electrode. The reactive circuit has a high-quality factor to negate a reactance of the electrode. There is no radio frequency (RF) match and an RF cable that couples the matchless plasma source to the electrode.

A system for sensing an electrical quantity may include a sensing stage configured to sense the electrical quantity and generate a sense signal indicative of the electrical quantity, wherein the electrical quantity is indicative of an electrical signal generated by a Class-DG amplifier configured to drive a load wherein the Class-DG amplifier has multiple signal-level common modes and a common-mode compensator configured to compensate for changes to a common-mode voltage of a differential supply voltage of the driver occurring when switching between signal-level common modes of the Class-DG amplifier.

A system for sensing an electrical quantity may include a sensing stage configured to sense the electrical quantity and generate a sense signal indicative of the electrical quantity, wherein the electrical quantity is indicative of an electrical signal generated by a Class-DG amplifier configured to drive a load wherein the Class-DG amplifier has multiple signal-level common modes and a common-mode compensator configured to compensate for changes to a common-mode voltage of a differential supply voltage of the driver occurring when switching between signal-level common modes of the Class-DG amplifier.

A small semiconductor device is provided. A semiconductor device with low power consumption is provided. A semiconductor device with a high degree of integration is provided. The semiconductor device includes a first transistor, an insulating layer over the first transistor, a conductive layer, and a gate driver; part of the conductive layer is provided to be embedded in the insulating layer; the gate driver includes a second transistor and a third transistor; the second transistor and the third transistor are stacked and provided over the first transistor; the second transistor and the third transistor each contain a metal oxide in a channel formation region; one of a source and a drain of the second transistor and one of a source and a drain of the third transistor are electrically connected to a gate of the first transistor through the conductive layer; the gate driver is supplied with a first potential and a second potential; and the gate driver has a function of selecting the first potential or the second potential and supplying the selected potential to the gate of the first transistor.

A logarithmic amplifier includes programmable gain amplifiers each having a different gain, wherein an input of each of the programmable gain amplifiers is coupled to an input of the logarithmic amplifier; and a summing circuit having inputs coupled to a corresponding output of each of the programmable gain amplifiers and an output coupled to an output of the logarithmic amplifier, wherein the summing circuit generates a logarithmic transfer function having piecewise linear segments.

In the field of audio amplifiers, the prior art for high output power levels is now to use class D technology. In this technology, audio signals are converted into a pulsed signal. An audio amplifier 1 is proposed, with a modulator section 4 for accepting an input signal and outputting two intermediate signals, wherein the modulator section 4 is designed to generate the intermediate signals by modulating the input signal, with an amplifier section 8 for accepting the two intermediate signals and outputting two amplified signals, wherein the amplifier section 8 is designed to generate the two amplified signals by amplifying the two intermediate signals, the amplifier section having two power stages 11;12, with an end section 21 for accepting the two amplified signals and for outputting an output signal for a loudspeaker device 2, wherein the audio amplifier 1 can be switched between parallel operation and bridge operation.

This application relates to Class D amplifier circuits. A modulator controls a Class D output stage based on a modulator input signal (Dm) to generate an output signal (Vout) which is representative of an input signal (Din). An error block, which may comprise an ADC, generates an error signal (ε) from the output signal and the input signal. In various embodiments the extent to which the error signal (ε) contributes to the modulator input signal (Dm) is variable based on an indication of the amplitude of the input signal (Din). The error signal may be received at a first input of a signal selector block. The input signal may be received at a second input of the signal selector block. The signal selector block may be operable in first and second modes of operation, wherein in the first mode the modulator input signal is based at least in part on the error signal; and in the second mode the modulator input signal is based on the digital input signal and is independent of the error signal. The error signal can be used to reduce distortion at high signal levels but is not used at low signal levels and so the noise floor at low signal levels does not depend on the component of the error block.