This application relates to Class D amplifier circuits. A modulator controls a Class D output stage based on a modulator input signal (Dm) to generate an output signal (Vout) which is representative of an input signal (Din). An error block, which may comprise an ADC, generates an error signal (ε) from the output signal and the input signal. In various embodiments the extent to which the error signal (ε) contributes to the modulator input signal (Dm) is variable based on an indication of the amplitude of the input signal (Din). The error signal may be received at a first input of a signal selector block. The input signal may be received at a second input of the signal selector block. The signal selector block may be operable in first and second modes of operation, wherein in the first mode the modulator input signal is based at least in part on the error signal; and in the second mode the modulator input signal is based on the digital input signal and is independent of the error signal. The error signal can be used to reduce distortion at high signal levels but is not used at low signal levels and so the noise floor at low signal levels does not depend on the component of the error block.

A system may include an analog loop filter comprising a plurality of analog integrators, the analog loop filter configured to receive an analog signal input and a feedback output signal, at least one sampler for sampling outputs of the analog integrators, a second loop filter coupled between an output of an analog pulse-width modulation driver and a digital pulse-width modulation controller, wherein the second loop filter comprises at least one integrator and is configured to receive sampled outputs of the analog integrators from the at least one sampler and receive a feedback pulse-width modulation signal from the analog pulse-width modulation driver, and a correction subsystem configured to apply a non-linear function to a signal path of the second loop filter in order to compensate for non-linearity introduced as a result of sampling outputs of the analog integrators.

A device includes a first ramp generator having a first ramp generator output configured to provide a first ramp, a second ramp generator having a second ramp generator output configured to provide a second ramp, and a third ramp generator having a third ramp generator output configured to provide a third ramp. The first ramp is a sawtooth voltage waveform having a first common mode voltage and a first peak-to-peak voltage. The second ramp is a sawtooth voltage waveform having a second common mode voltage and a second peak-to-peak voltage. The third ramp is a sawtooth voltage waveform having a third common mode voltage and a third peak-to-peak voltage. A frequency of the second ramp is approximately equal to a frequency of the third ramp, and the frequency of the third ramp is approximately double a frequency of the first ramp.

A single printed-circuit board of a class-D amplifier includes an input ground, an output ground, an input amplifying circuit, a modulation circuit, an output amplifying circuit, and an output filter, a solid pattern, a first feedback circuit, and a second feedback circuit. The solid pattern of the output ground extends into all regions of the input amplifying circuit, the modulation circuit, the output amplifying circuit and the output filter. The first feedback circuit executes a feedback where a voltage at a first connecting point is negatively fed back to an inverting input of the input amplifying circuit. The second feedback circuit executes a feedback where a voltage at a second connecting point is negatively fed back to a non-inverting input of the input amplifying circuit.

In some embodiments, a window circuit for an audio amplification system can include a pulse train generator configured to generate a train of rectangular pulses having M amplitude values, with the quantity M being an integer greater than 1, and M-1 accumulators arranged in series to transform the train of rectangular pulses into an output that is representative of an M-th order window. In some embodiments, such a window circuit can be utilized for a calibration circuit that includes a gain adjustment circuit configured to generate a correction signal to compensate for a gain variation of an audio amplifier based at least in part on a window of frequency at or about a frequency of a calibration tone applied to the audio amplifier.

A hybrid class-D amplifier is provided. The hybrid class-D amplifier includes a digital-to-analog conversion (DAC) input stage circuit, a loop filter circuit electrically coupled to the DAC input stage circuit, a quantizer circuit electrically coupled to the loop filter circuit, an output stage circuit electrically coupled to the quantizer circuit, and a feedback circuit electrically coupled between the output stage circuit and the loop filter circuit. The DAC input stage circuit converts a digital signal into an analog signal. The loop filter circuit generates a filtered signal according to the analog signal and a feedback signal. The quantizer circuit performs a quantization operation on the filtered signal to generate a quantized signal. The output stage circuit performs power amplification on the quantized signal to generate an output signal. The feedback circuit generates the feedback signal according to the output signal.

A control method of a minimum power input applicable to a wireless power transfer system including a power transmission unit and at least one power receiving unit is provided. The power transmission unit is electrically connected with a control voltage signal and an input voltage signal and accordingly generates the minimum power input. The power transmission unit transmits the minimum power input wirelessly through a wireless transmission to the at least one power receiving unit for receiving. By adjusting the input voltage signal, the duty ratio and resonant frequency of the control voltage signal, the present invention ensures an optimal power transmission efficiency of the wireless power transmission system. Moreover, parameters of a charge pump reservoir and gate driving circuit can be further designed in view of the trend feedback of its gate drive waveforms so as to optimize the effect of the proposed invention.

Example embodiments relate to push-pull class E amplifiers. One example push-pull class E amplifier includes an input configured for receiving a signal to be amplified. The push-pull class E amplifier also includes an output configured for outputting the signal after amplification. Additionally, the push-pull class E amplifier includes a printed circuit board having a first dielectric layer and a second dielectric layer. Further, the push-pull class E amplifier includes a first amplifying unit and a second amplifying unit. Yet further, the push-pull class E amplifier includes a balun, a capacitive unit, a first line segment, a second line segment, a third line segment, and a fourth line segment. The first line segment and the second line segment are arranged on the first dielectric layer. A combined length of the third line segment and the fourth line segment corresponds to a quarter wavelength of an operational frequency of the amplifier.

An amplifier system may include a first stage having a plurality of inputs configured to receive a differential pulse-width modulation input signal and generate an intermediate signal based on the differential pulse-width modulation input signal, a quantizer configured to generate a modulated signal based on the intermediate signal, a single-ended class-D output stage configured to generate a single-ended output signal as a function of the differential pulse-width modulation input signal, a feedback network configured to feed back the single-ended output signal to a first input of the plurality of inputs and to feed back a ground voltage to a second input of the plurality of inputs, a plurality of buffers, each particular buffer configured to receive a respective component of the differential pulse-width modulation input signal and generate a respective buffered component, and an input network coupled between the plurality of buffers and the first stage. Each particular buffer of the plurality of buffers may include a buffering subcircuit configured to buffer the respective component of the differential pulse-width modulation input signal associated with the particular buffer in order to generate the respective buffered component and a biasing subcircuit configured to limit a magnitude of the respective component of the differential pulse-width modulation input signal driven to circuitry of the buffering subcircuit for driving the respective buffered component.

An amplifier system may include a first stage having a plurality of inputs configured to receive a differential pulse-width modulation input signal and generate an intermediate signal based on the differential pulse-width modulation input signal, a quantizer configured to generate a modulated signal based on the intermediate signal, a single-ended class-D output stage configured to generate a single-ended output signal as a function of the differential pulse-width modulation input signal, a feedback network configured to feed back the single-ended output signal to a first input of the plurality of inputs and to feed back a ground voltage to a second input of the plurality of inputs, a plurality of buffers, each particular buffer configured to receive a respective component of the differential pulse-width modulation input signal and generate a respective buffered component, and an input network coupled between the plurality of buffers and the first stage. Each particular buffer of the plurality of buffers may include a buffering subcircuit configured to buffer the respective component of the differential pulse-width modulation input signal associated with the particular buffer in order to generate the respective buffered component and a biasing subcircuit configured to limit a magnitude of the respective component of the differential pulse-width modulation input signal driven to circuitry of the buffering subcircuit for driving the respective buffered component.