In the field of audio amplifiers, the prior art for high output power levels is now to use class D technology. In this technology, audio signals are converted into a pulsed signal.

An audio amplifier 1 is proposed, with a modulator section 4 for accepting an input signal and outputting two intermediate signals, wherein the modulator section 4 is designed to generate the intermediate signals by modulating the input signal, with an amplifier section 8 for accepting the two intermediate signals and outputting two amplified signals, wherein the amplifier section 8 is designed to generate the two amplified signals by amplifying the two intermediate signals, the amplifier section having two power stages 11;12, with an end section 21 for accepting the two amplified signals and for outputting an output signal for a loudspeaker device 2, wherein the audio amplifier 1 can be switched between parallel operation and bridge operation.

Described are concepts, systems, circuits and techniques directed toward methods and apparatus for generating one or more pulse width modulated (PWM) waveforms with the ability to dynamically control pulse width and phase with respect to a reference signal.

Amplifier architecture that allows low-cost class-D audio amplifiers to be compatible with ultrasonic signals, as well as loads presented by thin-film ultrasonic transducers. The amplifier architecture replaces the traditional capacitor used as an output filter in the class-D amplifier with the natural capacitance of the ultrasonic transducer load, and employs relative impedance magnitudes to create an under-damped low-pass filter that boosts voltage in the ultrasonic frequency band of interest. The amplifier architecture includes a secondary feedback loop to ensure that correct output voltage levels are provided.

Amplifier architecture that allows low-cost class-D audio amplifiers to be compatible with ultrasonic signals, as well as loads presented by thin-film ultrasonic transducers. The amplifier architecture replaces the traditional capacitor used as an output filter in the class-D amplifier with the natural capacitance of the ultrasonic transducer load, and employs relative impedance magnitudes to create an under-damped low-pass filter that boosts voltage in the ultrasonic frequency band of interest. The amplifier architecture includes a secondary feedback loop to ensure that correct output voltage levels are provided.

An amplifier, such as a Class D amplifier, having one or more feedback loops comprising a path from the input to the primary amplifier input, where the paths comprise a low pass filter and a compensator which is disabled when the primary amplifier clips.

An amplifier, such as a Class D amplifier, having one or more feedback loops comprising a path from the input to the primary amplifier input, where the paths comprise a low pass filter and a compensator which is disabled when the primary amplifier clips.

This switching power source 100 has: a switching output circuit 110 which drives an inductor current IL by turning on and off an upper switch 111 and a lower switch 112 and generates an output voltage VOUT from an input voltage PVDD; a lower current detection unit 210 which detects the inductor current IL flowing through the lower switch 112 during an ON-period of the lower switch 112 and acquires lower current feedback information Iinfo; an error amplifier 140 which outputs voltage feedback information Vinfo including information on an error between the output voltage VOUT (feedback voltage FB) and a reference voltage REF; an information synthesis unit 220 that generates synthesis feedback information VIinfo by synthesizing Iinfo with Vinfo; and an information holding unit 230 which samples Vinfo during the ON-period of the lower switch 112.

Systems and methods are provided for architectures for a digital class D driver that increase the power efficiency of the class D driver. In particular, systems and methods are provided for a digital class D driver having a feedback analog-to-digital converter (ADC) that can have a latency of 1 cycle or more than 1 cycle. A feedback ADC with a latency of 1 cycle or more is significantly lower power than a low latency feedback ADC. Systems and methods are disclosed for a power efficient digital class D driver architecture that allows for a latency of one or more cycles in the feedback ADC.

This switching power source 100 has: a switching output circuit 110 which drives an inductor current IL by turning on and off an upper switch 111 and a lower switch 112 and generates an output voltage VOUT from an input voltage PVDD; a lower current detection unit 210 which detects the inductor current IL flowing through the lower switch 112 during an ON-period of the lower switch 112 and acquires lower current feedback information Iinfo; an error amplifier 140 which outputs voltage feedback information Vinfo including information on an error between the output voltage VOUT (feedback voltage FB) and a reference voltage REF; an information synthesis unit 220 that generates synthesis feedback information VIinfo by synthesizing Iinfo with Vinfo; and an information holding unit 230 which samples Vinfo during the ON-period of the lower switch 112.

A power amplifier circuit includes a first amplifier that amplifies a first signal, and a second amplifier arranged subsequent to the first amplifier. The second amplifier amplifies a second signal that is based on an output signal of the first amplifier. The first amplifier performs class inverse-F operation, and the second amplifier performs class F operation.