An amplifier circuit includes: a Schmidt trigger having an input electrically coupled to an input of the amplifier circuit, a switching network electrically coupled to an output of the Schmidt trigger, an inductor electrically coupled to the switching network, a first resistor electrically coupled to the inductor, a capacitor electrically coupled to the first resistor, a first feedback circuit that provides a first feedback signal to the input of the Schmidt trigger based on a voltage at a first node electrically coupled to the first resistor and to the capacitor, a second resistor electrically coupled to the output of the amplifier circuit, a third resistor electrically coupled to the second resistor, and a second feedback circuit that provides a second feedback signal to the input of the Schmidt trigger based on a voltage at a second node electrically coupled to the second resistor and to the third resistor.

A driving circuit, an electronic device, and a controlling charging method, comprising: a first interface, used for receiving a direct-current signal inputted by an external power supply device; a second interface, used for receiving at least two pulse-width modulation (PWM) signals; and a processing circuit, used for overlaying and rectifying the direct-current signal and the at least two PWM signals so as to acquire a first direct-current signal, and outputting the first direct-current signal to a gate electrode of an MOS transistor.

A PWM modulator has a quantizer that generates a PWM output signal to speaker driver. When a first voltage swing range is supplied to the speaker driver, the quantizer analog gain is controlled to be a first gain value. When a second PWM drive voltage swing range is supplied to the speaker driver, the analog gain is controlled to be a second gain value. The first and second gain values of the analog gain of the quantizer cause the combined gain of the quantizer and driver to be approximately equal in the two modes. The quantizer has at least two gain-affecting measurable non-ideal characteristics. The quantizer is adjustable using measured first and second values to correct for first and second of the at least two non-ideal characteristics. The gain of the quantizer is calibratable while the quantizer is adjusted using the measured first and second measured values.

A PWM modulator has a quantizer that generates a PWM output signal to speaker driver. When a first voltage swing range is supplied to the speaker driver, the quantizer analog gain is controlled to be a first gain value. When a second PWM drive voltage swing range is supplied to the speaker driver, the analog gain is controlled to be a second gain value. The first and second gain values of the analog gain of the quantizer cause the combined gain of the quantizer and driver to be approximately equal in the two modes. The quantizer has at least two gain-affecting measurable non-ideal characteristics. The quantizer is adjustable using measured first and second values to correct for first and second of the at least two non-ideal characteristics. The gain of the quantizer is calibratable while the quantizer is adjusted using the measured first and second measured values.

The signal processing device includes: an offset adjuster; an amplitude adjuster; and a delay adjuster, wherein the offset adjuster adjusts the DC offset using a first parameter regarding the DC offset determined based on an output of the offset adjuster which is output when no signal is input to the signal processing circuit by the subtractor, the amplitude adjuster adjusts the amplitude using a second parameter regarding the amplitude determined based on (i) an output of the amplitude adjuster which is output when a first test signal is input to the signal processing circuit and (ii) the first test signal, and the delay adjuster adjusts the delay using a third parameter regarding the delay determined based on the difference signal that is an output of the subtractor when a second test signal is input to the signal processing circuit.

The signal processing device includes: an offset adjuster; an amplitude adjuster; and a delay adjuster, wherein the offset adjuster adjusts the DC offset using a first parameter regarding the DC offset determined based on an output of the offset adjuster which is output when no signal is input to the signal processing circuit by the subtractor, the amplitude adjuster adjusts the amplitude using a second parameter regarding the amplitude determined based on (i) an output of the amplitude adjuster which is output when a first test signal is input to the signal processing circuit and (ii) the first test signal, and the delay adjuster adjusts the delay using a third parameter regarding the delay determined based on the difference signal that is an output of the subtractor when a second test signal is input to the signal processing circuit.

The present disclosure provides an audio circuit capable of inhibiting a current when mute is deactivated. An output terminal of a class D amplifier circuit is connected to an electroacoustic conversion element through a low-pass filter. An output node of a bridge circuit is connected to the output terminal. An integrator integrates and outputs, in a non-mute period in which a mute control signal is negated, a difference between an input signal and a feedback signal corresponding to an output signal generated at the output terminal, and outputs a predetermined bias voltage in a mute period in which the mute control signal is asserted. A PWM comparator compares the output of the integrator with a periodic voltage. A driver switches, in the non-mute period, the bridge circuit according to an output of the PWM comparator, and fixes an output of the bridge circuit in the mute period.

A driving circuit is disclosed. The driving circuit includes a charging circuit, coupled between a voltage source and a load, configured to form a first current from the voltage source to the load; and a discharging circuit, coupled between the voltage source and the load, configured to form a second current from the load back to the voltage source.

A power amplifier is provided. The power amplifier comprises: a universal pulse converter configured to: receive at least one analog input; and modulate an in-phase component of the at least one analog input and a quadrature component of the at least one input signal; a processor configured to process the in-phase and quadrature components, the processor comprising: a clock configured to produce a clock signal; a pulse processor configured to remove non-essential information from the modulated in-phase and quadrature components; and a pulse converter configured to output a control signal based on a selected amplifier class; and a switching network configured to actuate one or more switches based on the control signal to output an amplified signal.

A pulse width modulated (PWM) amplifier includes a synchronization logic circuit having a first input configured to receive a bridge control signal and having a second input configured to receive a clock signal. The synchronization logic circuit is configured to provide a slope switch signal and a reference switch signal. The PWM amplifier includes a ramp generator having a first input configured to receive a first voltage supply and having a second input configured to receive a second voltage supply and having a third input configured to receive the reference switch signal and having a fourth input configured to receive the slope switch signal. The ramp generator is configured to provide a ramp signal having a first slope responsive to the slope switch signal in a first state and having a second slope responsive to the slope switch signal in a second state and to provide the clock signal.