A supply modulator is provided, having a first amplifier circuit configured to generate a first electrical signal, a second amplifier circuit configured to generate a second electrical signal, the first and second electrical signals being for driving an electrical load, and a control circuit electrically coupled to the first and second amplifier circuits wherein the control circuit is configured to generate a pulsed electrical signal and to supply an output control signal to the second amplifier circuit for controlling generation of the second electrical output signal, wherein the supply modulator is configured to operate in two modes of operation, for the first amplifier circuit to generate the first electrical signals in response to quiescent current of the first amplifier circuit, for the control circuit to generate a modulated electrical signal in accordance with a clock signal in one mode, and, for the second amplifier circuit to operate at different frequencies.

Methods and systems for power amplification of time varying envelope signals are disclosed herein. In one embodiment, a plurality of signals with constant envelope generated from the decomposition of the quantized version of a time varying envelope signal are individually amplified and then summed to form a desired time-varying envelope signal. Amplitude, phase and frequency characteristics of one or more of the constituent signals are controlled to provide the desired phase, frequency, and/or amplitude characteristics of the desired time varying envelope signal. In another embodiment, a time-varying envelope signal is decomposed into in-phase and quadrature components that are quantized and decomposed into a plurality of quasi constant or constant envelope constituent signals. The constituent signals are amplified, and then summed to construct an amplified version of the original time-varying envelope signal. The signal amplifiers may be Class A, B, AB, C, D, Class F or Class S amplifiers to provide high amplification efficiency.

A digital amplifier that minimizes and restricts an analog signal system and uses a feedback signal and a dither signal is achieved. A pulse width modulator that adjusts a pulse width of a digital signal, a switching circuit that amplifies an output signal from the pulse width modulator, and a feedback signal generation unit that generates a feedback signal based on an output signal from the switching circuit are included, the pulse width modulator adjusts the pulse width of the digital signal with reference to the feedback signal, and the feedback signal generation unit includes a first amplifier that outputs a first amplified signal in which a difference between the output signal from the switching circuit and one of a reference voltage and a dither signal is amplified and a second amplifier that amplifies a difference between the first amplified signal and the other of the dither signal and the reference voltage and outputs the amplified difference as the feedback signal.

A digital amplifier that minimizes and restricts an analog signal system and uses a feedback signal and a dither signal is achieved. A pulse width modulator that adjusts a pulse width of a digital signal, a switching circuit that amplifies an output signal from the pulse width modulator, and a feedback signal generation unit that generates a feedback signal based on an output signal from the switching circuit are included, the pulse width modulator adjusts the pulse width of the digital signal with reference to the feedback signal, and the feedback signal generation unit includes a first amplifier that outputs a first amplified signal in which a difference between the output signal from the switching circuit and one of a reference voltage and a dither signal is amplified and a second amplifier that amplifies a difference between the first amplified signal and the other of the dither signal and the reference voltage and outputs the amplified difference as the feedback signal.

An amplifying device includes a self-excited class D amplifier circuit and a band elimination filter. The self-excited class D amplifier circuit includes a modulation circuit that is configured to apply self-oscillating pulse modulation to an audio signal. The modulation circuit is configured to receive, from a signal generation circuit, a supply of a synchronizing signal with which the self-oscillation synchronizes. The band elimination filter is configured to reduce components that belong to a frequency band including a frequency of the synchronizing signal, in an output signal from the self-excited class D amplifier circuit.

Configurable amplifier systems are described in which the power supply rail of a linear amplifier, e.g., a class A amplifier, is modulated by a switching amplifier, e.g., a class D amplifier, that may also be configured to operate independently of the linear amplifier. Techniques are also described by which the standing current of the output stage of a linear amplifier is modulated based on the input signal to the linear amplifier or based on modulation of the power supply rail of the linear amplifier.

The present disclosure relates to Class D amplifier circuitry comprising: an input for receiving an input signal; first and second output nodes for driving a load connected between the first and second output nodes. A first driver stage is provided for switching the first node between a first supply rail and a second supply rail, and a second driver stage is provided for switching the second node between the first supply rail and the second supply rail. The Class D amplifier circuitry also includes first driver control circuitry configured to receive a first carrier wave and control the switching of the first driver stage based in part on the first carrier wave; second driver control circuitry configured to receive a second carrier wave and control the switching of the second driver stage based in part on the second carrier wave; and a carrier wave generator configured to provide the first carrier wave and the second carrier wave. A phase shift between the first carrier wave and the second carrier wave is adjustable responsive to a mode control signal.

A driver system may include a first n-type field-effect transistor coupled at its non-gate terminals between an output of the driver system and a first terminal of a supply voltage and configured to drive the output when the first n-type field-effect transistor is activated, a second n-type field-effect transistor coupled at its non-gate terminals between an output of the driver system and a second terminal of the supply voltage and configured to drive the output when the second n-type field-effect transistor is activated, a high-side capacitor coupled to the output of the driver system, and a low-side capacitor coupled to the second terminal of the supply voltage, wherein the high-side capacitor and the low-side capacitor are configured to track and correct for mismatches between a first resistance of the first n-type field-effect transistor and a second resistance of the second n-type field-effect transistor.

A power amplifier circuit includes a lower transistor having a first terminal, a second terminal connected to ground, and a third terminal, wherein a first power supply voltage is supplied to the first terminal, and an input signal is supplied to the third terminal; a first capacitor; an upper transistor having a first terminal, a second terminal connected to the first terminal of the lower transistor via the first capacitor, and a third terminal, wherein a second power supply voltage is supplied to the first terminal, an amplified signal is outputted to an output terminal from the first terminal, and a driving voltage is supplied to the third terminal; a first inductor that connects the second terminal of the upper transistor to ground; a voltage regulator circuit; and at least one termination circuit that short-circuits an even-order harmonic or odd-order harmonic of the amplified signal to ground potential.

A power amplifier circuit includes a lower transistor having a first terminal, a second terminal connected to ground, and a third terminal, wherein a first power supply voltage is supplied to the first terminal, and an input signal is supplied to the third terminal; a first capacitor; an upper transistor having a first terminal, a second terminal connected to the first terminal of the lower transistor via the first capacitor, and a third terminal, wherein a second power supply voltage is supplied to the first terminal, an amplified signal is outputted to an output terminal from the first terminal, and a driving voltage is supplied to the third terminal; a first inductor that connects the second terminal of the upper transistor to ground; a voltage regulator circuit; and at least one termination circuit that short-circuits an even-order harmonic or odd-order harmonic of the amplified signal to ground potential.