A negative feedback system architecture and a loop filter thereof are provided. The negative feedback system architecture includes a loop filter, a pulse width modulation circuit, and a driver. The loop filter includes a three-stage series integrator for receiving a signal and outputting the filtered signal. The loop filter has three in-bandwidth poles and at least two in-bandwidth zeros. The pulse width modulation circuit is electrically connected to the loop filter for receiving the filtered signal and modulating it into a pulse width modulation signal to output. The driver is electrically connected to the pulse width modulation circuit and the loop filter for receiving the pulse width modulation signal to generate an output signal to drive a load device, and the output signal is fed back to the loop filter.

In a general aspect, a circuit can include an input circuit configured to receive an input signal, and an amplifier circuit coupled with the input circuit. The amplifier circuit can include an amplifier, and first and second feedback paths. The first feedback path can be from a positive output to a negative input of the amplifier, and the second feedback path can be from a negative output to a positive input of the first amplifier. The circuit can also include a loop circuit configured to provide a local feedback loop for the first amplifier and configured to control current flow into the positive input of the first amplifier and current flow into the negative input of the first amplifier. The circuit can also include a control circuit that is configured to enable the loop circuit in response to a magnitude of the input signal exceeding a threshold.

An audio driver circuit includes a modulator circuit configured to receive an audio input signal and produce a first modulated digital pulse signal. The first modulated digital pulse signal has a magnitude that switches between a supply power voltage and a supply ground voltage. The audio driver circuit also includes a switched driver circuit coupled to the modulator circuit to receive the first modulated digital pulse signal and configured to provide a second modulated digital pulse signal for driving an MOS (metal oxide semiconductor) output transistor. The second modulated digital pulse signal has a same timing pattern as the first modulated digital pulse signal and has a magnitude that tracks linearly with the magnitude of the audio input signal.

A class D power amplifier with novel design is provided. The amplifier includes an input stage, a periodic signal generator, a comparator, a power output stage, and a boost circuit. The input stage is coupled to a first supply voltage. The periodic signal generator generates a periodic signal and a reference signal. The power output stage is coupled to a second supply voltage. The boost circuit compares an output of the input stage with the reference signal, and thereby adjusts a value of the second supply voltage. The value of the second supply voltage is larger than a value of the first supply voltage. The reference signal is proportional to an amplitude of the periodic signal, and the amplitude of the periodic signal is determined by the value of the second supply voltage.

A class D power amplifier with novel design is provided. The amplifier includes an input stage, a periodic signal generator, a comparator, a power output stage, and a boost circuit. The input stage is coupled to a first supply voltage. The periodic signal generator generates a periodic signal and a reference signal. The power output stage is coupled to a second supply voltage. The boost circuit compares an output of the input stage with the reference signal, and thereby adjusts a value of the second supply voltage. The value of the second supply voltage is larger than a value of the first supply voltage. The reference signal is proportional to an amplitude of the periodic signal, and the amplitude of the periodic signal is determined by the value of the second supply voltage.

Certain aspects of the present disclosure are generally directed to circuitry and techniques for voltage-to-current conversion. For example, certain aspects provide a circuit for signal amplification including a first amplifier; a first transistor, a gate of the first transistor being coupled to an output of the first amplifier and a drain of the first transistor being coupled to an output node of circuit; a first resistive element coupled between a first input node of the circuit and an input of the first amplifier; a second amplifier; a second transistor, a gate of the second transistor being coupled to an output of the second amplifier and a drain of the second transistor being coupled to the output node of circuit; and a second resistive element coupled between a second input node of the circuit and an input of the second amplifier.

Methods and systems for aligning amplification gains in a plurality of interconnected devices are disclosed. The method includes receiving by each device limiter gain attenuations and brownout gain attenuations broadcasted by the plurality of devices and selecting the maximum brownout gain attenuation and the maximum limiter gain attenuation. The method includes determining a total attenuation as a sum of the maximum brownout attenuation gain and the maximum limiter attenuation gain. The method includes receiving a frame synchronization signal and adjusting the amplification gain by applying the total attenuation responsive to the frame synchronization signal.

Methods and systems for aligning amplification gains in a plurality of interconnected devices are disclosed. The method includes receiving by each device limiter gain attenuations and brownout gain attenuations broadcasted by the plurality of devices and selecting the maximum brownout gain attenuation and the maximum limiter gain attenuation. The method includes determining a total attenuation as a sum of the maximum brownout attenuation gain and the maximum limiter attenuation gain. The method includes receiving a frame synchronization signal and adjusting the amplification gain by applying the total attenuation responsive to the frame synchronization signal.

This switching power source 100 has: a switching output circuit 110 which drives an inductor current IL by turning on and off an upper switch 111 and a lower switch 112 and generates an output voltage VOUT from an input voltage PVDD; a lower current detection unit 210 which detects the inductor current IL flowing through the lower switch 112 during an ON-period of the lower switch 112 and acquires lower current feedback information Iinfo; an error amplifier 140 which outputs voltage feedback information Vinfo including information on an error between the output voltage VOUT (feedback voltage FB) and a reference voltage REF; an information synthesis unit 220 that generates synthesis feedback information VIinfo by synthesizing Iinfo with Vinfo; and an information holding unit 230 which samples Vinfo during the ON-period of the lower switch 112.

An output driver with slew rate control includes an output transistor that includes a control terminal coupled to a switching input signal, a drain node coupled to the output node for coupling to a load device, and a source node coupled to a reference voltage. The output driver also has a slew control circuit including a current source coupled in series at a connection node with parallelly connected first switch transistor and second switch transistor. The connection node is coupled to the control terminal of the output transistor. The first switch transistor has a control terminal coupled to the switching input signal. The second switch transistor has a control terminal that is coupled to either the switching input signal or a dynamically modulated switching input signal, depending on a current direction at the output node.