A switched mode amplifier system may include a switched mode amplifier having an amplifier input coupled to an output of an analog integrator and an amplifier output and include a calibration system. The calibration system may be configured to force the input of the analog integrator to a fixed known input value, force the amplifier output to a fixed known duty cycle, measure an analog signal generated at the output of the analog integrator in response to forcing the input of the analog integrator to the fixed value, determine an offset of the switched mode amplifier system based on the analog signal, and correct for the offset.

It is disclosed an amplifier for driving a capacitive load, comprising an input terminal adapted to receive an input voltage signal, an output terminal adapted to drive the capacitive load, a linear amplification stage, switching amplification stage, a capacitor, a first switch and a measurement and control circuit. The measurement and control circuit is configured to: measure the value of the current generated at the output from the linear amplification stage and generate a driving voltage signal of the switching amplification stage; generate the first switching signal to open the first switch and generate an enabling signal to enable the operation of at least part of the switching amplification stage; generate the first switching signal to close the first switch and generate the enabling signal to disable the operation of the switching amplification stage; generate the first switching signal to open the first switch.

A semiconductor device includes: a first buffer at which a predetermined signal is input and that outputs a first output signal; a second buffer at which an inverted signal of the predetermined signal is input and that outputs a second output signal; and a short circuit detection circuit that, in accordance with a potential difference between the first output signal and the second output signal, outputs a short circuit evaluation signal evaluating whether or not there is a ground fault in at least one of a first terminal at an output side of the first buffer or a second terminal at an output side of the second buffer or evaluating whether or not there is a short circuit between the first terminal and the second terminal.

A semiconductor device includes: a first buffer at which a predetermined signal is input and that outputs a first output signal; a second buffer at which an inverted signal of the predetermined signal is input and that outputs a second output signal; and a short circuit detection circuit that, in accordance with a potential difference between the first output signal and the second output signal, outputs a short circuit evaluation signal evaluating whether or not there is a ground fault in at least one of a first terminal at an output side of the first buffer or a second terminal at an output side of the second buffer or evaluating whether or not there is a short circuit between the first terminal and the second terminal.

High frequency amplifier circuitry includes a common-source first transistor to amplify a high-frequency input signal, a common-gate second transistor cascade-connected to the first transistor, to amplify a signal amplified by the first transistor to generate an output signal, a first inductor connected between a source of the first transistor and a first reference potential node, a second inductor connected between a drain of the second transistor and a second reference potential node, and non-linear compensation circuitry connected to a connection node of the first transistor and the second transistor, to compensate for non-linearity of the output signal to the high-frequency input signal. The non-linear compensation circuitry has first rectifier circuitry, a first resistor, a second resistor, second rectifier circuitry, first capacitor and second capacitor.

An audio amplifier has an analog current source amplifier and a class D amplifier. The analog current source amplifier is active in a first mode to drive a speaker when an audio signal has smaller amplitude. The class D amplifier is active in a second mode to drive the speaker when the audio signal has larger amplitude. Other aspects are also described and claimed.

A class-D amplifier according to an embodiment includes a PWM modulator, a first output transistor group that includes two transistors complementarily operating and includes a first connection point between the two transistors as an output terminal, a second output transistor group that includes two transistors complementarily operating and includes a second connection point between the two output transistors as an output terminal, and a selector configured to selectively provide a PWM pulse signal to one of the first output transistor group and the second output transistor group. A system that includes the second output transistor group, a low-pass filter, and a load connected to the low-pass filter configures a series resonance circuit.

Methods and systems for aligning amplification gains in a plurality of interconnected devices are disclosed. The method includes receiving by each device limiter gain attenuations and brownout gain attenuations broadcasted by the plurality of devices and selecting the maximum brownout gain attenuation and the maximum limiter gain attenuation. The method includes determining a total attenuation as a sum of the maximum brownout attenuation gain and the maximum limiter attenuation gain. The method includes receiving a frame synchronization signal and adjusting the amplification gain by applying the total attenuation responsive to the frame synchronization signal.

Methods and systems for aligning amplification gains in a plurality of interconnected devices are disclosed. The method includes receiving by each device limiter gain attenuations and brownout gain attenuations broadcasted by the plurality of devices and selecting the maximum brownout gain attenuation and the maximum limiter gain attenuation. The method includes determining a total attenuation as a sum of the maximum brownout attenuation gain and the maximum limiter attenuation gain. The method includes receiving a frame synchronization signal and adjusting the amplification gain by applying the total attenuation responsive to the frame synchronization signal.

An amplifier having one or more channels where each channel includes a two half bridges (a master and slave sub-channel). The sub-channels can be connected either in parallel or in a full-bridge configuration via internal switches that route signals to a pair of speaker jacks. One switch in the amplifier has a first position that selectively connects the outputs of the master and slave sub-channel to the same input of the speaker load so that the two sub-channels will drive the speaker load in parallel and a second position where the output of the slave sub-channel is connected to another input of the speaker load so that the master sub-channel and the slave sub-channel will drive the speaker load in a Full-bridge configuration. A second switch has a first position that connects a second input of the speaker load to ground or reference potential of the sub-channels when the speaker load is to be driven in parallel and a second position that is a No-connect position that is used when the speaker load is driven in the Full-bridge configuration and a ground potential is not to be connected to the speaker.