An electronic apparatus is described. The apparatus includes a circuit element configured to output a signal comprising a modulated frequency component. The apparatus also includes a filter arrangement comprising first, second and third notch filter arrangements, wherein each of the first and second notch filter arrangements comprise a first series inductor, and a series shunt configuration comprising a second inductor and a capacitor coupled in series and the third notch filter arrangement comprises a series inductor and a shunt capacitor, wherein each of the notch filter arrangements are configured to generate a notch in a frequency response to attenuate the output signal at a frequency of the modulated frequency component.

An electronic apparatus is described. The apparatus includes a circuit element configured to output a signal comprising a modulated frequency component. The apparatus also includes a filter arrangement comprising first, second and third notch filter arrangements, wherein each of the first and second notch filter arrangements comprise a first series inductor, and a series shunt configuration comprising a second inductor and a capacitor coupled in series and the third notch filter arrangement comprises a series inductor and a shunt capacitor, wherein each of the notch filter arrangements are configured to generate a notch in a frequency response to attenuate the output signal at a frequency of the modulated frequency component.

Embodiments of the present invention provide a power amplifier, a radio remote unit RRU, and a base station. A multiphase pulse width modulator performs modulation to generate N multiphase pulse-width modulation PWM signals. The multiphase pulse-width modulation PWMn signal may be amplified. The multiphase pulse-width modulation PWMn signal may be filtered and a combination may be performed at a drain or a collector of a power amplifier transistor. According to the new radio frequency amplifier in accordance with the disclosure, envelope feeding loop inductance can be effectively reduced, so that video bandwidth is increased and DPD correction performance is improved.

A bias circuit includes a current source to generate a reference current, a temperature compensation portion in an off-state in an initial start period in response to a first control signal, and in an on-state in a normal driving period, subsequent to the initial start period, and to receive a first current of the reference current, and a bias output portion to generate a warm up current based on the reference current in the initial start period and to generate a bias current based on a second current, which is lower than the reference current by an amount of the first current, in the normal driving period.

An audio system has an amplifier having first and second power stages configurable to drive a speaker, each power stage having two transistors connected in series. Each of one or more analog-to-digital converters is connected to measure a corresponding voltage drop across a corresponding transistor. A processor is connected to characterize the operation of the audio system based on the measured voltage drops. The ADC(s) and the processor can be used during start-up and/or run-time operations of the audio system to determine or detect transistor ON resistance, system lag time, speaker current, open-load faults, shorted-load faults, and short-to-Vdd/Vss faults. To avoid errors, the processor determines or detects and avoids under-drive conditions, high-frequency conditions, ripple-current periods, and lag-time periods while characterizing the system operations.

A gate driver circuit comprises a sensor, an amplifier, a regulator and a gate driver. The sensor is configured to sense a collector-emitter voltage and includes a first resistor and a second resistor connected in series, a high voltage diode connected between the series connected first and second resistors and a first capacitor connected parallel to the second resistor. The amplifier is configured to amplify a sensor output voltage and includes a non-inverting operational amplifier controlled by means of a plurality of resistors, a voltage follower connected to an output terminal of the non-inverting operational amplifier through a first diode and a third resistor connected across the first diode and the voltage follower. The regulator is configured to regulate a regulator output voltage based on an amplifier voltage. The gate driver is configured to connect/disconnect the regulator output voltage to the base terminal of the BJT.

A system may include a charge pump configured to boost an input voltage of the charge pump to an output voltage greater than the input voltage, a current mode control loop for current mode control of a power amplifier powered by the output voltage of the charge pump, and a controller configured to, in a current-limiting mode of the controller, control an output power of the charge pump to ensure that an input current of the charge pump is maintained below a current limit, control the power amplifier by placing the power amplifier into a high-impedance mode during the current-limiting mode, and control state variables of a loop filter of the current mode control loop during the current-limiting mode.

Configurable amplifier systems are described in which the power supply rail of a linear amplifier, e.g., a class A amplifier, is modulated by a switching amplifier, e.g., a class D amplifier, that may also be configured to operate independently of the linear amplifier. Techniques are also described by which the standing current of the output stage of a linear amplifier is modulated based on the input signal to the linear amplifier or based on modulation of the power supply rail of the linear amplifier.

A Class D amplifier comprising a control circuit configured to receive an audio input signal and derive first, second and third PWM switching control signals therefrom, being supplied to respectively first, second and third switches of a driver, the first and second switches being serially arranged between first and second supply voltages, and having a common node coupled to an output terminal. The driver comprises a DC level shifter being configured to provide a reference voltage to a reference terminal in at least first and second states of operation, said reference voltage including a DC component at least substantially equidistant between the first and second supply voltages. Said third switch being included in a shunt path between the output and the reference terminal.

Sampler circuitry, having: an input node which receives an input voltage signal; a primary current path connected between high and low voltage supply nodes; a secondary current path connected between high and low voltage supply nodes; current mirror circuitry; and load circuitry having sampler switches which sample a current signal, where the input node is defined along the primary current path, the primary current path configured to carry a primary current dependent on the input voltage signal; the current mirror circuitry includes a primary side and a secondary side, the primary side connected along the primary current path and the secondary side connected along the secondary current path so that a secondary current dependent on the primary current is caused to flow along the secondary current path; and the load circuitry is connected along the secondary current path so that the secondary current at least partly forms the current signal.