An inductor is provided, comprising: a first ferrite core piece and a second ferrite core piece, each of which are made of substantially similar materials, exhibit desired electromagnetic properties, and which are fashioned in a substantially similar manner and shape, and wherein each of the first and second ferrite core pieces comprises a substantially planar mating surface, a center post, and a wire core assembly channel, and wherein a first substantially planar mating surface of the first ferrite core piece is adapted to planarly mate with a second substantially planar mating surface of the second ferrite core piece; and a wire core assembly adapted to be substantially self-locating and self-centering about a first or second center post when located in a respective first or second wire core assembly channel.

An inductor is provided, comprising: a first ferrite core piece and a second ferrite core piece, each of which are made of substantially similar materials, exhibit desired electromagnetic properties, and which are fashioned in a substantially similar manner and shape, and wherein each of the first and second ferrite core pieces comprises a substantially planar mating surface, a center post, and a wire core assembly channel, and wherein a first substantially planar mating surface of the first ferrite core piece is adapted to planarly mate with a second substantially planar mating surface of the second ferrite core piece; and a wire core assembly adapted to be substantially self-locating and self-centering about a first or second center post when located in a respective first or second wire core assembly channel.

An inductor is provided, comprising: a first ferrite core piece and a second ferrite core piece, each of which are made of substantially similar materials, exhibit desired electromagnetic properties, and which are fashioned in a substantially similar manner and shape, and wherein each of the first and second ferrite core pieces comprises a substantially planar mating surface, a center post, and a wire core assembly channel, and wherein a first substantially planar mating surface of the first ferrite core piece is adapted to planarly mate with a second substantially planar mating surface of the second ferrite core piece; and a wire core assembly adapted to be substantially self-locating and self-centering about a first or second center post when located in a respective first or second wire core assembly channel.

An inductor is provided, comprising: a first ferrite core piece and a second ferrite core piece, each of which are made of substantially similar materials, exhibit desired electromagnetic properties, and which are fashioned in a substantially similar manner and shape, and wherein each of the first and second ferrite core pieces comprises a substantially planar mating surface, a center post, and a wire core assembly channel, and wherein a first substantially planar mating surface of the first ferrite core piece is adapted to planarly mate with a second substantially planar mating surface of the second ferrite core piece; and a wire core assembly adapted to be substantially self-locating and self-centering about a first or second center post when located in a respective first or second wire core assembly channel.

An inductor is provided, comprising: a first ferrite core piece and a second ferrite core piece, each of which are made of substantially similar materials, exhibit desired electromagnetic properties, and which are fashioned in a substantially similar manner and shape, and wherein each of the first and second ferrite core pieces comprises a substantially planar mating surface, a center post, and a wire core assembly channel, and wherein a first substantially planar mating surface of the first ferrite core piece is adapted to planarly mate with a second substantially planar mating surface of the second ferrite core piece; and a wire core assembly adapted to be substantially self-locating and self-centering about a first or second center post when located in a respective first or second wire core assembly channel.

Embodiments described herein relate to an envelope tracking system that uses a single-bit digital signal to encode an analog envelope tracking control signal, or envelope tracking signal for brevity. In certain embodiments, the envelope tracking system can estimate or measure the amplitude of the baseband signal. The envelope tracking system can further estimate the amplitude of the envelope of the RF signal. The system can convert the amplitude of the envelope signal to a single-bit digital signal, typically at a higher, oversample rate. The single-bit digital signal can be transmitted in, for example, a low-voltage differential signaling (LVDS) format, from a transceiver to an envelope tracker. An analog-to-digital converter (ADC or A/D) can convert the single-bit digital signal back to an analog envelope signal. Moreover, a driver can increase the power of the A/D output envelope signal to produce an envelope-tracking supply voltage for a power amplifier.

Embodiments described herein relate to an envelope tracking system that uses a single-bit digital signal to encode an analog envelope tracking control signal, or envelope tracking signal for brevity. In certain embodiments, the envelope tracking system can estimate or measure the amplitude of the baseband signal. The envelope tracking system can further estimate the amplitude of the envelope of the RF signal. The system can convert the amplitude of the envelope signal to a single-bit digital signal, typically at a higher, oversample rate. The single-bit digital signal can be transmitted in, for example, a low-voltage differential signaling (LVDS) format, from a transceiver to an envelope tracker. An analog-to-digital converter (ADC or A/D) can convert the single-bit digital signal back to an analog envelope signal. Moreover, a driver can increase the power of the A/D output envelope signal to produce an envelope-tracking supply voltage for a power amplifier.

Disclosed herein is an amplification circuit that outputs an output signal formed by amplifying a differential signal between a first input terminal and a second input terminal using an operating amplifier and a plurality of resistors, the amplification circuit including an adjustment circuit configured to adjust a frequency property of the output signal for an in-phase alternating current signal input between the first input terminal and the second input terminal. The adjustment circuit is connected to one input terminal of the first input terminal and the second input terminal through one or more resistors, the adjustment circuit includes a capacitor part whose capacitance is set to be variable, and the adjustment is realized through variable setting of the capacitance of the capacitor part.

In a Class-D amplifier, first/second ratios and first/second RC time constants are sequentially matched by trimming. An integrator is coupled to differential first/second paths. The first/second ratios are of a feedback resistor to an input resistor in the first/second paths. R's of the first/second RC time constants are the resistors of the first/second matched ratios. C's of the first/second RC time constants are integrating capacitors in the first/second path. For each of multiple power rails, a ramp amplitude is determined based on a sensed voltage. Concurrently, the driver stage is switched from first to second power rails and quantizer switched from first to second ramp amplitudes to achieve constant combined quantizer/driver stage gain. Based on a sensed load current, an IR drop is determined for a respective output impedance of the driver stage and added to a loop filter output to compensate for the respective output impedance.

A switched-capacitor power amplifier comprising a plurality of cells and methods for its operation are described. Switched signal lines switch supply to respective capacitors. Switches connect respective signal lines to a first supply and switches connect respective signal lines to a second supply. Pairs of switches on each signal line are switched so that one is switched off whilst the other is switched on. In a full amplitude mode, operation of the switches provides an output having a peak determined by the first supply. A switch signal line is provided between nodes in respective signal lines, a switch being provided in the switch signal line. In a half amplitude mode, switch is switched at the radio frequency in the other direction to that of switches connecting the signal lines to respective ones of the first and second supplies with the other switches being kept open.