A current control circuit controls a bias current that is supplied to an amplifier transistor that amplifies a radio-frequency signal and includes a node, a constant current source circuit that supplies a first current to the node, and a variable current source circuit that supplies a second current to the node, based on a result of comparison between a potential of the node and a reference potential. The node outputs a control current including the first current and the second current for controlling the bias current.

According to at least one example of the disclosure, a power amplifier system is provided comprising an amplifying transistor configured to amplify a radio frequency signal, a bias circuit configured to provide a bias voltage to the amplifying transistor, and a clamp circuit for protecting the power amplifier system by absorbing a current flowing through the amplifying transistor when the clamp circuit is switched on. The clamp circuit is connected at a bias node between the bias circuit and the amplifying transistor and includes a clamp transistor and a clamp diode, the clamp diode having one end connected to a collector of the clamp transistor at the bias node and another end connected to a base of the clamp transistor.

A distributed power amplifier includes radio frequency (RF) input and output terminals. A first field effect transistor (FET) is coupled at a first gate terminal to the RF input terminal and at a first drain terminal to the RF output terminal. The first FET has a first periphery and a first source terminal electrically connected to ground potential. A second FET has a second periphery smaller than the first periphery. The second FET has a second gate terminal electrically coupled to the first gate terminal through a first inductor, a second drain terminal electrically coupled to the first drain terminal through a second inductor, and a second source terminal electrically connected to the ground potential. A drain voltage terminal, which excludes a resistive element, is electrically coupled to a drain bias network through which a drain bias voltage is applied to the first drain terminal and the second drain terminal.

A phase-synchronized RF power generator includes: an RF power amplifier for amplifying an RF power signal; a first directional coupler; an isolator for adjusting impedance mismatch generated by the first directional coupler, and transferring the RF power signal transferred by the first directional coupler to the output terminal; a second directional coupler for transferring part of the feedback signal transferred by the first directional coupler to be compared with a frequency of a reference signal provided by a crystal oscillator, and transferring rest of the feedback signal to a feedback loop; a digital phase shifter for adjusting a phase of the feedback signal transferred by the second directional coupler at predetermined intervals; an analog phase shifter for continuously adjusting the phase of the feedback signal discretely adjusted by the digital phase shifter; and a frequency comparator.

An amplifier includes a semiconductor die and a substrate that is distinct from the semiconductor die. The semiconductor die includes a III-V semiconductor substrate, a first RF signal input terminal, a first RF signal output terminal, and a transistor (e.g., a GaN FET). The transistor has a control terminal electrically coupled to the first RF signal input terminal, and a current-carrying terminal electrically coupled to the first RF signal output terminal. The substrate includes a second RF signal input terminal, a second RF signal output terminal, circuitry coupled between the second RF signal input terminal and the second RF signal output terminal, and an electrostatic discharge (ESD) protection circuit. The amplifier also includes a connection electrically coupled between the ESD protection circuit and the control terminal of the transistor. The substrate may be another semiconductor die (e.g., with a driver transistor and/or impedance matching circuitry) or an integrated passive device.

In one embodiment, a dual-mode power amplifier that can operate in different modes includes: a first pair of metal oxide semiconductor field effect transistors (MOSFETs) to receive and pass a constant envelope signal; a second pair of MOSFETs to receive and pass a variable envelope signal, where first terminals of the first pair of MOSFETs are coupled to first terminals of the second pair of MOSFETs, and second terminals of the first pair of MOSFETs are coupled to. second terminals of the second pair of MOSFETs; and a shared MOSFET stack coupled to the first pair of MOSFETs and the second pair of MOSFETs.

A compensator compensates for the distortions of a power amplifier circuit. A power amplifier neural network (PAN) is trained to model the power amplifier circuit using pre-determined input and output signal pairs that characterize the power amplifier circuit. Then a compensator is trained to pre-distort a signal received by the PAN. The compensator uses a neural network trained to optimize a loss between a compensator input and a PAN output, and the loss is calculated according to a multi-objective loss function that includes one or more time-domain loss function and one or more frequency-domain loss functions. The trained compensator performs signal compensation to thereby output a pre-distorted signal to the power amplifier circuit.

In some embodiments, stability in power amplifiers can be achieved under high in-band voltage standing wave ratio condition, with an amplifier circuit that includes an amplifier having a first stage and a second stage, with each stage including an input and an output, such that the output of the first stage is coupled to the input of the second stage. The amplifier circuit further includes a stabilizing circuit implemented on the input side of the second stage and configured to provide stability in operation of the amplifier under a high in-band voltage standing wave ratio condition.

Disclosed is a reconfigurable power amplifier having a 2.sup.N−1 number of input-side reconfigurable quadrature couplers connected in a tree structure, wherein a 2.sup.(N−1) number of the input-side reconfigurable quadrature couplers have coupler output terminals, and a root of the tree structure is one of the input-side reconfigurable quadrature couplers having a main input terminal. Also included is a 2.sup.N−1 number of output-side reconfigurable quadrature couplers connected in a tree structure, wherein a 2.sup.(N−1) number of the output-side reconfigurable quadrature couplers have coupler input terminals, and a root of the tree structure is one of the output-side reconfigurable quadrature couplers having a main output terminal. Further included is a 2.sup.N number of constituent amplifiers divided into amplifier pairs having amplifier input terminals connected to corresponding ones of the coupler output terminals and having amplifier output terminals coupled to corresponding ones of the coupler input terminals.

An active electronic device that enables bidirectional communication over a single antenna or path is disclosed. The device may be characterized by a forward path (from an input to an antenna port) offering high gain, and a reverse path (to a receiver port) that can be configured as an finite impulse response (“FIR”) filter. An amplifier of the device is disclosed, the amplifier allowing for tuning of output resistance using passive mixers.