Disclosed herein are circuits, devices and methods that address challenges associated with power amplifier systems. A power amplifier system includes two or more fast error amplifiers coupled to corresponding power amplifiers. The fast error amplifiers are configured to generate envelope tracking signals based on a signal envelope, the envelope tracking signals modifying a DC-DC regulated voltage from a DC-DC converter to more efficiently operate the power amplifiers. By splitting the envelope tracking between two or more fast error amplifiers and amplification between corresponding two or more power amplifiers, the power, frequency or bandwidth, linearity, signal-to-noise ratio, efficiency, or the like of the power amplifier system can be improved. Wireless communications configurations with such power amplifier systems can provide uplink carrier aggregation and/or cellular signals based on standards and protocols that require increased bandwidth and/or power.

The present invention relates to a multi-stage and feed forward compensated complimentary current field effect transistor amplifiers, enabling a charge-based approach that takes advantage of the exponential properties incurred in sub-threshold operation. A plurality of complimentary pairs of novel current field effect transistors are connected in series to form a multi-stage amplifier.

The present invention relates to a novel and inventive compound device structure for a low noise current amplifier or trans-impedance amplifier. The trans-impedance amplifier includes an amplifier portion, which converts current input into voltage using a complimentary pair of novel n-type and p-type current field-effect transistors (NiFET and PiFET) and a bias generation portion using another complimentary pair of NiFET and PiFET. Trans-impedance of NiFET and PiFET and its gain may be configured and programmed by a ratio of width (W) over length (L) of source channel over the width (W) over length (L) of drain channel (W/L of source channel/W/L of drain channel).

A buffer amplifier circuit includes a buffer amplifier including a first differential amplifier having a first active load and a second differential amplifier having a second active load and a feedback circuit configured to feed an output signal of an output terminal of the buffer amplifier back to one of the first and second active loads using differential switch signals and an input signal of the buffer amplifier to enhance a slew rate of the output signal.

The present invention relates to a control circuit for producing a first and second control signals in order for a clock signal to break before making delays, comprising a first and second AND gates for receiving clock signals, first and second alignment blocks that receives output signals from the first and second AND gates for providing alignment prior to transmitting the first and second control signals, and generate the first and second control signals, respectively.

A power amplifier circuit includes a differential to single-ended converter, a gain stage circuit, a driver stage circuit, and an output stage circuit connected in series, and a bias circuit connected to a bias voltage port of the gain stage circuit for adjusting a bias voltage of the gain stage circuit. The bias voltage is adjustable to ensure low power consumption, improve the efficiency of the power amplifier circuit and prevent process, voltage and temperatures from affecting the performance of the power amplifier circuit.

A two-stage operational amplifier is provided to comprise a bias voltage generator, a first stage operational amplifier and a second stage operational amplifier, wherein the first stage operational amplifier comprises a folded cascode amplifier circuit and a cross coupling load, the cross coupling load is coupled to a load differential pair in the folded cascode amplifier circuit, the cross coupling load comprises two transistors, the two transistors in the cross coupling load and two transistors in the load differential pair constitute two current mirror structures, which are cross coupled. In the solution, the cross coupling load is added to the load differential pair in the folded cascode amplifier circuit, to increase gain of the two-stage operational amplifier by using positive feedback and negative conductance gain enhancement technology; while parameters of MOSFETs in the folded cascode amplifier circuit are properly set to reduce noise of the two-stage operational amplifier.

A system includes a class D amplifier and a current steering digital-to-analog converter (DAC) directly connected to the class D amplifier. The system also includes a common mode servo circuit coupled to a node interconnecting the current steering DAC to the class D amplifier. The common servo circuit amplifies a difference between a common mode signal determined from the node and a reference voltage and generates a feedback current to the node based on the amplified difference. A feed-forward common-mode compensation circuit is included to reduce an alternating current (AC) ripple from the class D amplifier. The feed-forward common-mode compensation circuit includes first and second resistors coupled to respective outputs of the class D amplifier. A current mirror is coupled to the first and second resistors and is configured to sink a current from the node to ground that approximates a common mode feedback current of the class D amplifier.

A driver circuit includes a first operational amplifier circuit, a second operational amplifier circuit, and at least one power switching circuit is provided. The first operational amplifier circuit receives a first input signal and generates a first output signal according to the first input signal. The second operational amplifier circuit receives a second input signal and generates a second output signal according to the second input signal. The at least one power switching circuit is coupled to the first operational amplifier circuit and the second operational amplifier circuit, and configured to switch at least one power supply for both the first operational amplifier circuit and the second operational amplifier circuit.

Disclosed herein are circuits, devices and methods that address challenges associated with power amplifier systems. A power amplifier system includes two or more fast error amplifiers coupled to corresponding power amplifiers. The fast error amplifiers are configured to generate envelope tracking signals based on a signal envelope, the envelope tracking signals modifying a DC-DC regulated voltage from a DC-DC converter to more efficiently operate the power amplifiers. By splitting the envelope tracking between two or more fast error amplifiers and amplification between corresponding two or more power amplifiers, the power, frequency or bandwidth, linearity, signal-to-noise ratio, efficiency, or the like of the power amplifier system can be improved. Wireless communications configurations with such power amplifier systems can provide uplink carrier aggregation and/or cellular signals based on standards and protocols that require increased bandwidth and/or power.