A low drop-out (LDO) voltage regulator circuit includes a power transistor having a control terminal configured to receive a control signal and an output terminal coupled to an output node. A current regulation loop senses current flowing through the power transistor and modulates the control signal to cause the power transistor to output a constant current to the output node. A voltage regulation loop senses voltage at the output node and modulates the control signal to cause the power transistor to deliver current to the output node so that an output voltage at the output node is regulated. The current regulation loop includes a bipolar transistor connected to the control terminal of the power transistor, where a base terminal of the bipolar transistor is driven by a signal dependent on a difference between the sensed current flowing through the power transistor and a reference.

An apparatus includes a radio-frequency (RF) circuit, which includes a power amplifier coupled to receive an RF input signal and to provide an RF output signal in response to a modified bias signal. The RF circuit further includes a bias path circuit coupled to modify a bias signal as a function of a characteristic of an input signal to generate the modified bias signal. The bias path circuit provides the modified bias signal to the power amplifier.

A power amplifier circuit includes lower-stage and upper-stage differential amplifying pairs, a combiner, first and second inductors, and first and second capacitors. First and second signals are input into the lower-stage differential amplifying pair. The upper-stage differential amplifying pair outputs first and second amplified signals. The combiner combines the first and second amplified signals. The lower-stage differential amplifying pair includes first and second transistors. A supply voltage is supplied to the collectors of the first and second transistors. The first and second signals are supplied to the bases of the first and second transistors. The upper-stage differential amplifying pair includes third and fourth transistors. A supply voltage is supplied to the collectors of the third and fourth transistors. The emitters of the third and fourth transistors are grounded via the first and second inductors and are connected to the first and second transistors via the first and second capacitors.

The disclosure relates to a pre-5th-generation (5G) or 5G communication system to be provided for supporting higher data rates beyond 4th-generation (4G) communication system such as long term evolution (LTE). An operation method of a device for upconversion in a wireless communication system is provided. The method includes receiving a first local oscillator (LO) signal, generating a second LO signal, based on the first LO signal and cross-coupled latches, receiving an input signal, generating an upconverted frequency, based on the second LO signal and the input signal, generating an output signal obtained by processing a harmonic component included in the upconverted frequency, and transmitting the generated output signal.

A system includes a pixel that emits light based on a signal provided to the pixel. The system may also include a buffer circuit having a differential pair stage, a cascade stage, and an output stage. The differential pair stage may receive a common mode voltage signal via a first switch in response to the first switch receiving a first signal that causes the first switch to close. The differential pair stage may couple a capacitor to the output stage via a second switch that operate based on a second signal, such that the capacitor reduces an offset provided by one or more circuit components in the differential pair stage, the cascade stage, the output stage, or any combination thereof. The differential pair stage may output the common mode voltage to the pixel via the output stage in response to the first signal being present.

A semiconductor amplifier circuit has a driver that outputs a drive signal corresponding to an input signal and switches drive capability of the drive signal in accordance with a logic of an instruction signal, an instruction signal setting unit that sets the logic of the instruction signal in accordance with whether the input signal satisfies a predetermined condition, and an output circuit that comprises a control terminal to which the drive signal is input and an output terminal that outputs a signal obtained by amplifying the input signal.

An amplifier circuit includes, a first transistor and a first resistor connected in series between a power supply voltage and an output terminal. A second transistor and a second resistor are connected in series between the output terminal and a ground reference voltage. There is a first operational amplifier and a second operational amplifier. A first detection current corresponding to a voltage drop across first resistor is generated. A second detection current corresponding to a voltage drop across the second resistor is generated. A first replication circuit subtracts the second detection current from the first detection current. A third resistor conducts the current obtained by subtracting the second detection current from the first detection current.

A DC-DC converter according to an embodiment is a DC-DC converter for generating an output voltage VOUT according to a reference voltage VREF, and includes a fully differential amplifier that outputs a first differential output signal and a second differential output signal according to a differential input using the reference voltage VREF and the output voltage VOUT, a pulse width modulation signal generation circuit that generates a pulse width modulation signal based on the first differential output signal Vout1 and the second differential output signal Vout2, and a driver that outputs a driving signal obtained by waveform-shaping the pulse width modulation signal.

A low drop-out (LDO) voltage regulator circuit includes a power transistor having a control terminal configured to receive a control signal and an output terminal coupled to an output node. A current regulation loop senses current flowing through the power transistor and modulates the control signal to cause the power transistor to output a constant current to the output node. A voltage regulation loop senses voltage at the output node and modulates the control signal to cause the power transistor to deliver current to the output node so that an output voltage at the output node is regulated. The current regulation loop includes a bipolar transistor connected to the control terminal of the power transistor, where a base terminal of the bipolar transistor is driven by a signal dependent on a difference between the sensed current flowing through the power transistor and a reference.

A fully differential rail-to-rail-output amplifier includes a differential input inverter pair, folded cascode pair, class AB control pair, and class AB output rail-to-rail pair. A drain associated with the folded cascode pair is operatively coupled to the class AB control pair, and the drain associated with the folded cascode pair is unconnected to the current source associated with the class AB control pair. A method of providing fully differential rail-to-rail-output amplification includes coupling a folded cascode pair operatively to a differential input inverter pair, coupling a drain associated with the folded cascode pair operatively to a class AB control pair, and coupling a class AB output rail-to-rail pair operatively to the class AB control pair.