In described examples, a circuit includes a first current mirror circuit. The first current mirror circuit is coupled to a power input terminal. A first stage is coupled to the first current mirror circuit, and a second stage is coupled to the first stage and to the first current mirror circuit. An amplifier is coupled to the first and second stages. The amplifier has first and second input terminals. The first input terminal is coupled to the first stage, and the second input terminal is coupled to the second stage. A second current mirror circuit is coupled to the first stage, the second stage and the amplifier.

An amplification apparatus includes a bias circuit for supplying a bias voltage, and an amplification circuit to which the bias voltage is supplied from the bias circuit. The bias circuit includes a first current source for increasing/decreasing a first current depending on the bias voltage, and a first MOSFET with first polarity through which the first current flows, to output a first voltage from a connection between the first current source and the first MOSFET; a second current source for outputting a constant current as a second current, and a second MOSFET with second polarity through which the second current flows, to output a second voltage from a connection between the second current source and the second MOSFET; and a voltage comparator for increasing/decreasing the bias voltage such that the first and second voltages become equal, based on a difference between the first and second voltages.

A current mirror circuit includes: a first transistor and a second transistor connected in series, a third transistor and a fourth transistor connected in series; and further includes: a reference voltage source, a fifth transistor, and a control module connected between the reference voltage source and the fifth transistor. A current mirror is formed by the third transistor and the fourth transistor together with the first transistor and the second transistor, to produce a mirror current at a drain of the third transistor according to a current source coupled to a drain of the first transistor; the control module is configured to control the fifth transistor to operate in the linear region.

A current mirror circuit includes: a first transistor and a second transistor connected in series, a third transistor and a fourth transistor connected in series; and further includes: a reference voltage source, a fifth transistor, and a control module connected between the reference voltage source and the fifth transistor. A current mirror is formed by the third transistor and the fourth transistor together with the first transistor and the second transistor, to produce a mirror current at a drain of the third transistor according to a current source coupled to a drain of the first transistor; the control module is configured to control the fifth transistor to operate in the linear region.

A source follower with an input node and an output node includes a first transistor, a second transistor, and a DC (Direct Current) tracking circuit. The first transistor has a control terminal, a first terminal coupled to a first node, and a second terminal coupled to a second node. The second transistor has a control terminal, a first terminal coupled to a ground voltage, and a second terminal coupled to the first node. The DC tracking circuit sets the second DC voltage at the second node to a specific level. The specific level is determined according to the first DC voltage at the first node. The output node of the source follower is coupled to the first node.

A source follower with an input node and an output node includes a first transistor, a second transistor, and a DC (Direct Current) tracking circuit. The first transistor has a control terminal, a first terminal coupled to a first node, and a second terminal coupled to a second node. The second transistor has a control terminal, a first terminal coupled to a ground voltage, and a second terminal coupled to the first node. The DC tracking circuit sets the second DC voltage at the second node to a specific level. The specific level is determined according to the first DC voltage at the first node. The output node of the source follower is coupled to the first node.

An envelope tracking (ET) current bias circuit includes a rectifying circuit, a phase compensation circuit, and a voltage/current conversion circuit. The rectifying circuit is configured to detect an envelope voltage from a radio frequency (RF) signal. The phase compensation circuit is configured to compensate for a phase of the envelope voltage in which the phase thereof is delayed in the rectifying circuit to output a phase compensated enveloped voltage. The voltage/current conversion circuit is configured to convert the phase compensated envelope voltage into an ET bias current.

An envelope tracking (ET) current bias circuit includes a rectifying circuit, a phase compensation circuit, and a voltage/current conversion circuit. The rectifying circuit is configured to detect an envelope voltage from a radio frequency (RF) signal. The phase compensation circuit is configured to compensate for a phase of the envelope voltage in which the phase thereof is delayed in the rectifying circuit to output a phase compensated enveloped voltage. The voltage/current conversion circuit is configured to convert the phase compensated envelope voltage into an ET bias current.

The present invention relates to a continuous time linear equalizer comprising a first signal path comprising a high pass filter and a first controllable transconductance unit and a second signal path comprising a second controllable transconductance unit. The continuous time linear equalizer comprises a summation node configured to receive complementary current summation signals of the first transconductance unit and the second transconductance unit. The high pass filter comprises a first port configured to receive an input signal, a second port coupled to a control port of the first transconductance unit and a third port coupled to the summation node. The invention is notably also directed to a corresponding method and a corresponding design structure.

The present invention relates to a continuous time linear equalizer comprising a first signal path comprising a high pass filter and a first controllable transconductance unit and a second signal path comprising a second controllable transconductance unit. The continuous time linear equalizer comprises a summation node configured to receive complementary current summation signals of the first transconductance unit and the second transconductance unit. The high pass filter comprises a first port configured to receive an input signal, a second port coupled to a control port of the first transconductance unit and a third port coupled to the summation node. The invention is notably also directed to a corresponding method and a corresponding design structure.