Disclosed herein are amplification systems that are dynamically biased based on a signal indicative of differential envelope of an input radio-frequency (RF) signal being amplified. The amplification systems include a cascode amplifier configured to amplify the RF signal to generate an output RF signal when one of the transistors of the cascode amplifier is biased by a combination of the input RF signal and a biasing signal while the other transistor of the cascode amplifier is biased by a processed differential envelope signal. The cascode amplifier also receives a combination of a processed differential envelope signal and a supply voltage to generate the output RF signal. The biasing signal can improve or enhance the linearity of amplification systems.

Disclosed herein are amplification systems that are dynamically biased based on a signal indicative of differential envelope of an input radio-frequency (RF) signal being amplified. The amplification systems include a cascode amplifier configured to amplify the RF signal to generate an output RF signal when one of the transistors of the cascode amplifier is biased by a combination of the input RF signal and a biasing signal while the other transistor of the cascode amplifier is biased by a processed differential envelope signal. The cascode amplifier also receives a combination of a processed differential envelope signal and a supply voltage to generate the output RF signal. The biasing signal can improve or enhance the linearity of amplification systems.

A circuit includes a first signal swapper including a first terminal coupled to a first current source, a second terminal coupled to a second current source, a third terminal coupled to a first current terminal of a first transistor, and a fourth terminal coupled to a third current terminal of a second transistor. The first signal swapper couples the first and second terminals to the third and fourth terminals responsive to a first control signal. First and second switches couple to a gate of the first transistor. The first switch receives the input oscillation signal and the second switch receives a first reference voltage. Third and fourth switches couple to a gate of the second transistor. The third switch receives the input oscillation signal and the fourth switch receives the first reference voltage. A second signal swapper couples to the first signal swapper and to the first and second transistors.

A circuit having (A) a transistor; (B) a bias circuit for providing setting a bias current for the transistor, the bias current having a current level in accordance with a reference current fed to the bias circuit; and (C) a bias current level controller, comprising: (i) a plurality of switches, each one of the switches comprises: a MOS FET and a GaN FET connected in a cascode configuration; and (ii) current source circuitry, comprising a plurality of current sources, each one of the current sources being connected between a voltage source and a corresponding one of the plurality of switches, the current source circuit combining currents produced by the current source in response a binary control signal fed to a gate of the MOS FET, the combined current providing the reference current fed to the bias circuit.

A circuit having (A) a transistor; (B) a bias circuit for providing setting a bias current for the transistor, the bias current having a current level in accordance with a reference current fed to the bias circuit; and (C) a bias current level controller, comprising: (i) a plurality of switches, each one of the switches comprises: a MOS FET and a GaN FET connected in a cascode configuration; and (ii) current source circuitry, comprising a plurality of current sources, each one of the current sources being connected between a voltage source and a corresponding one of the plurality of switches, the current source circuit combining currents produced by the current source in response a binary control signal fed to a gate of the MOS FET, the combined current providing the reference current fed to the bias circuit.

A signal amplifying system having an oscillator and an amplifying circuit. The oscillator has a first resistor with a first resistance R1 and a first capacitor with a first capacitance C1, and generates an oscillating signal having a frequency f which equals to k1/(R1*C1), k1 is a first proportional parameter. The amplifying circuit has an input terminal to receive an input signal and amplifies the input signal under the control of the oscillating signal. The amplifying circuit has a second resistor with a second resistance R2 and a second capacitor with a second capacitance C2. The amplifying circuit has a 3 dB bandwidth W.sub.3 dB which equals to k2/(R2*C2), k2 is a second proportional parameter. In this signal amplifying system, the product of the first resistance R1 and the first capacitance C1 is proportional to the product of the second resistance R2 and the second capacitance C2.

A signal amplifying system having an oscillator and an amplifying circuit. The oscillator has a first resistor with a first resistance R1 and a first capacitor with a first capacitance C1, and generates an oscillating signal having a frequency f which equals to k1/(R1*C1), k1 is a first proportional parameter. The amplifying circuit has an input terminal to receive an input signal and amplifies the input signal under the control of the oscillating signal. The amplifying circuit has a second resistor with a second resistance R2 and a second capacitor with a second capacitance C2. The amplifying circuit has a 3 dB bandwidth W.sub.3 dB which equals to k2/(R2*C2), k2 is a second proportional parameter. In this signal amplifying system, the product of the first resistance R1 and the first capacitance C1 is proportional to the product of the second resistance R2 and the second capacitance C2.

An offset drift compensation circuit for correcting offset drift that changes with temperature. In one example, offset drift compensation circuit includes a low temperature offset compensation circuit and a high temperature offset circuit. The low temperature offset compensation circuit is configured to compensate for drift in offset at a first rate below a selected temperature. The high temperature offset compensation circuit is configured to compensate for drift in offset at a second rate above the selected temperature. The first rate is different from the second rate.

The present invention relates to a continuous time linear equalizer comprising a first signal path comprising a high pass filter and a first controllable transconductance unit and a second signal path comprising a second controllable transconductance unit. The continuous time linear equalizer comprises a summation node configured to receive complementary current summation signals of the first transconductance unit and the second transconductance unit. The high pass filter comprises a first port configured to receive an input signal, a second port coupled to a control port of the first transconductance unit and a third port coupled to the summation node. The invention is notably also directed to a corresponding method and a corresponding design structure.

A circuit includes a first signal swapper including a first terminal coupled to a first current source, a second terminal coupled to a second current source, a third terminal coupled to a first current terminal of a first transistor, and a fourth terminal coupled to a third current terminal of a second transistor. The first signal swapper couples the first and second terminals to the third and fourth terminals responsive to a first control signal. First and second switches couple to a gate of the first transistor. The first switch receives the input oscillation signal and the second switch receives a first reference voltage. Third and fourth switches couple to a gate of the second transistor. The third switch receives the input oscillation signal and the fourth switch receives the first reference voltage. A second signal swapper couples to the first signal swapper and to the first and second transistors.