Patent classifications
H03F3/345
POWER AMPLIFIER CIRCUIT
The present disclosure provides an amplifier circuit that includes one or more amplifier stages, each of the one or more amplifier stages including a complementary transistor configuration. The complementary transistor configuration includes an NMOS transistor and a PMOS transistor. The NMOS transistor is electrically coupled in parallel to the PMOS transistor. The amplifier circuit further includes an output amplifier stage electrically coupled to an output of the one or more amplifier stages, the output amplifier stage including a non-complementary transistor configuration including one or more NMOS transistors or PMOS transistors.
LOW NOISE BANDGAP REFERENCE ARCHITECTURE
In described examples, a circuit includes a first current mirror circuit. The first current mirror circuit is coupled to a power input terminal. A first stage is coupled to the first current mirror circuit, and a second stage is coupled to the first stage and to the first current mirror circuit. An amplifier is coupled to the first and second stages. The amplifier has first and second input terminals. The first input terminal is coupled to the first stage, and the second input terminal is coupled to the second stage. A second current mirror circuit is coupled to the first stage, the second stage and the amplifier.
LOW NOISE BANDGAP REFERENCE ARCHITECTURE
In described examples, a circuit includes a first current mirror circuit. The first current mirror circuit is coupled to a power input terminal. A first stage is coupled to the first current mirror circuit, and a second stage is coupled to the first stage and to the first current mirror circuit. An amplifier is coupled to the first and second stages. The amplifier has first and second input terminals. The first input terminal is coupled to the first stage, and the second input terminal is coupled to the second stage. A second current mirror circuit is coupled to the first stage, the second stage and the amplifier.
Ratiometric biasing for high impedance capacitive sensing
A biasing circuit for a capacitive sensor includes a capacitive sensor element configured to produce a sensor voltage at a sense node, and a preamplifier connected to the sense node and configured to amplify the sensor voltage. The biasing circuit has an auxiliary amplifier connected between an output of the preamplifier and the sense node and configured to set a DC component of an input voltage for the preamplifier to a ratiometric DC bias voltage.
Ratiometric biasing for high impedance capacitive sensing
A biasing circuit for a capacitive sensor includes a capacitive sensor element configured to produce a sensor voltage at a sense node, and a preamplifier connected to the sense node and configured to amplify the sensor voltage. The biasing circuit has an auxiliary amplifier connected between an output of the preamplifier and the sense node and configured to set a DC component of an input voltage for the preamplifier to a ratiometric DC bias voltage.
SINGLE-ENDED TRANS-IMPEDANCE AMPLIFIER (TIA) FOR ULTRASOUND DEVICE
An ultrasound circuit comprising a single-ended trans-impedance amplifier (TIA) is described, The TIA is coupled to an ultrasonic transducer to amplify an electrical signal generated by the ultrasonic transducer in response to receiving an ultrasound signal. The TEA is followed by further processing circuitry configured to filter, amplify, and digitize the signal produced by the TIA.
AMPLIFICATION SYSTEM WITH DIFFERENTIAL ENVELOPE-BASED BIAS
Disclosed herein are amplification systems that are dynamically biased based on a signal indicative of differential envelope of an input radio-frequency (RF) signal being amplified. The amplification systems include a cascode amplifier configured to amplify the RF signal to generate an output RF signal when one of the transistors of the cascode amplifier is biased by a combination of the input RF signal and a biasing signal while the other transistor of the cascode amplifier is biased by a processed differential envelope signal. The cascode amplifier also receives a combination of a processed differential envelope signal and a supply voltage to generate the output RF signal. The biasing signal can improve or enhance the linearity of amplification systems.
AMPLIFICATION SYSTEM WITH DIFFERENTIAL ENVELOPE-BASED BIAS
Disclosed herein are amplification systems that are dynamically biased based on a signal indicative of differential envelope of an input radio-frequency (RF) signal being amplified. The amplification systems include a cascode amplifier configured to amplify the RF signal to generate an output RF signal when one of the transistors of the cascode amplifier is biased by a combination of the input RF signal and a biasing signal while the other transistor of the cascode amplifier is biased by a processed differential envelope signal. The cascode amplifier also receives a combination of a processed differential envelope signal and a supply voltage to generate the output RF signal. The biasing signal can improve or enhance the linearity of amplification systems.
CASCODE COMMON SOURCE TRANSIMPEDANCE AMPLIFIERS FOR ANALYTE MONITORING SYSTEMS
A biosensor for an analyte monitoring system. In one embodiment, the biosensor includes a cascode common source transimpedance amplifier circuit, an analog to digital converter, and an output circuit. The cascode common source transimpedance amplifier circuit is configured to receive an electrical current generated by an electrochemical reaction of an analyte on a test strip. The cascode common source transimpedance amplifier circuit is also configured to convert the electrical current to an analog voltage signal. The analog to digital converter is configured to convert the analog voltage signal to a digital voltage signal. The output circuit is configured to transmit a signal indicating a measured level of the analyte based on the digital voltage signal.
ENVELOPE TRACKING CURRENT BIAS CIRCUIT AND POWER AMPLIFYING DEVICE
An envelope tracking (ET) current bias circuit includes a rectifying circuit, a phase compensation circuit, and a voltage/current conversion circuit. The rectifying circuit is configured to detect an envelope voltage from a radio frequency (RF) signal. The phase compensation circuit is configured to compensate for a phase of the envelope voltage in which the phase thereof is delayed in the rectifying circuit to output a phase compensated enveloped voltage. The voltage/current conversion circuit is configured to convert the phase compensated envelope voltage into an ET bias current.