H03F3/345

Sensor mirror circuitry with reduced error compounding

Sense mirror circuitry receives a voltage signal having values corresponding to a magnitude of a measured current. Responsive to the values falling within a first predefined range, the sense mirror circuitry outputs a current at a first predefined magnitude that corresponds to the first predefined range. Responsive to the values falling within a second predefined range, the sense mirror circuitry outputs a current at a second predefined magnitude different than the first predefined magnitude and that corresponds to the second predefined range.

Sensor mirror circuitry with reduced error compounding

Sense mirror circuitry receives a voltage signal having values corresponding to a magnitude of a measured current. Responsive to the values falling within a first predefined range, the sense mirror circuitry outputs a current at a first predefined magnitude that corresponds to the first predefined range. Responsive to the values falling within a second predefined range, the sense mirror circuitry outputs a current at a second predefined magnitude different than the first predefined magnitude and that corresponds to the second predefined range.

Low-headroom constant current source for high-current applications

A low-headroom current driver does not use an op amp or resistor. A sensing transistor having its source connected to a drain of an output transistor senses variations in an output current. The gate, source, and drain voltages of the sensing transistor are mirrored to a sense mirror transistor to control a sense current. The sense current is mirrored to a reference source transistor to generate a mirrored sense current. An error between the mirrored sense current and a fixed reference current is stored as charge on an error-storing capacitor. The stored error charge creates a negative-feedback compensation current that adjusts a gate voltage generated by a feedback-driving transistor. The adjusted gate voltage controls the gate of the output transistor to compensate for the sensed variation in output current. The sensing current is also compensated using a sense-mirror tail transistor connected to the sense mirror transistor.

Low-Headroom Constant Current Source for High-Current Appliations

A low-headroom current driver does not use an op amp or resistor. A sensing transistor having its source connected to a drain of an output transistor senses variations in an output current. The gate, source, and drain voltages of the sensing transistor are mirrored to a sense mirror transistor to control a sense current. The sense current is mirrored to a reference source transistor to generate a mirrored sense current. An error between the mirrored sense current and a fixed reference current is stored as charge on an error-storing capacitor. The stored error charge creates a negative-feedback compensation current that adjusts a gate voltage generated by a feedback-driving transistor. The adjusted gate voltage controls the gate of the output transistor to compensate for the sensed variation in output current. The sensing current is also compensated using a sense-mirror tail transistor connected to the sense mirror transistor.

PVT ROBUST CLOSED LOOP CMOS BIAS FOR LINEAR POWER AMPLIFIER
20170104458 · 2017-04-13 ·

A biasing device for direct current (DC) biasing a linear power amplifier that comprises multiple linear power amplifier circuits that are ideally identical to each other; wherein the biasing device may include a replica circuit that is a replica of a linear power amplifier circuit of the multiple linear power amplifier circuits; and a bias control circuit; wherein the bias control circuit is configured to feed the replica circuit with one or more DC biasing signals thereby maintaining at a constant value a replica DC current that is consumed by the replica circuit, and maintaining at a fixed value a replica DC voltage of a replica output node of the replica circuit; and wherein the replica circuit is coupled the multiple linear power amplifier circuits and is configured to supply DC voltage bias signals that force each linear power amplifier circuit of the multiple linear power amplifier circuits to consume a linear power amplifier circuit DC current that equals the replica DC current, when the linear power amplifier circuit is fed with a linear power amplifier DC voltage that either equals the replica DC voltage or differs from the replica DC voltage by a fraction of the replica DC voltage.

PVT ROBUST CLOSED LOOP CMOS BIAS FOR LINEAR POWER AMPLIFIER
20170104458 · 2017-04-13 ·

A biasing device for direct current (DC) biasing a linear power amplifier that comprises multiple linear power amplifier circuits that are ideally identical to each other; wherein the biasing device may include a replica circuit that is a replica of a linear power amplifier circuit of the multiple linear power amplifier circuits; and a bias control circuit; wherein the bias control circuit is configured to feed the replica circuit with one or more DC biasing signals thereby maintaining at a constant value a replica DC current that is consumed by the replica circuit, and maintaining at a fixed value a replica DC voltage of a replica output node of the replica circuit; and wherein the replica circuit is coupled the multiple linear power amplifier circuits and is configured to supply DC voltage bias signals that force each linear power amplifier circuit of the multiple linear power amplifier circuits to consume a linear power amplifier circuit DC current that equals the replica DC current, when the linear power amplifier circuit is fed with a linear power amplifier DC voltage that either equals the replica DC voltage or differs from the replica DC voltage by a fraction of the replica DC voltage.

Amplifier circuit, corresponding device and method

An amplifier circuit includes a first input stage with a differential input transistor pair and a second gain stage having an output node coupled to a load. A node in the first gain stage is coupled to the output node in the second gain stage. A feedback line couples the output node to the control node of a first transistor of the differential input transistor pair. Current mirror circuitry is coupled to a current flow path through a further transistor in the second gain stage and includes a sensing node configured to produce a sensing signal indicative of the current supplied to the load. The sensing signal at the sensing node is directly fed back to the control node of the first transistor of the differential input transistor pair to provide a zero in the loop transfer function that is matched to and tracks and cancels out a load-dependent pole.

Receiver control circuit and terminal

Disclosed are a receiver control circuit and a terminal. The receiver control circuit includes: a smart power amplifier module, a coder-decoder, and a receiver. The smart power amplifier module is electrically connected to the receiver by a first switch module. The first switch module includes a first switch component unit that is formed by a metal oxide semiconductor field-effect transistor (MOSFET). The first switch module further includes a first follower unit, where the first follower unit is configured to keep an unchanged voltage difference between a gate electrode of the MOSFET of the first switch component unit and a drain electrode thereof, and a gate electrode voltage of the MOSFET of the first switch component unit is greater than a drain electrode voltage thereof. The coder-decoder is electrically connected to the receiver by the second switch module. The second switch module includes a second switch component unit.

Receiver control circuit and terminal

Disclosed are a receiver control circuit and a terminal. The receiver control circuit includes: a smart power amplifier module, a coder-decoder, and a receiver. The smart power amplifier module is electrically connected to the receiver by a first switch module. The first switch module includes a first switch component unit that is formed by a metal oxide semiconductor field-effect transistor (MOSFET). The first switch module further includes a first follower unit, where the first follower unit is configured to keep an unchanged voltage difference between a gate electrode of the MOSFET of the first switch component unit and a drain electrode thereof, and a gate electrode voltage of the MOSFET of the first switch component unit is greater than a drain electrode voltage thereof. The coder-decoder is electrically connected to the receiver by the second switch module. The second switch module includes a second switch component unit.

Power-save mode for fixed-frequency DC-DC converter

In a circuit for DC-DC voltage converters, an amplifier has first and second inputs coupled to a reference voltage terminal and an output voltage terminal, respectively. A comparator has first and second inputs coupled to an amplifier output and a switching terminal, respectively. A logic circuit has inputs coupled to the comparator output and a clock terminal. A driver circuit has first and second inputs coupled to first and second logic outputs, respectively. A first transistor having a first control terminal coupled to the first driver output is coupled between a supply voltage terminal and the switching terminal. A second transistor is coupled between the switching terminal and a ground terminal, and has a second control terminal coupled to the second driver output. A threshold detection circuit is configured to provide a threshold signal responsive to a current through the second transistor crossing a current threshold.