A differential amplifier circuit includes: a control current source supplying a control current; paired bipolar transistors; an a variable resistance circuit including: a series circuit of a first resistor and a second resistor having an identical resistance, the series circuit electrically connected between a first terminal and a second terminal of the variable resistance circuit; a first field effect transistor (FET) having a source and a drain being electrically connected to emitters of the paired bipolar transistors, respectively; and a second FET having a drain, a gate being electrically connected to the drain thereof, the gate of the first FET, and a control terminal of variable resistance circuit, a source being electrically connected to a connection node between the first resistor and the second resistor, wherein the control current source adjusts the control current to allow transconductance of the second FET to be kept constant.

A differential amplifier circuit includes: a control current source supplying a control current; paired bipolar transistors; an a variable resistance circuit including: a series circuit of a first resistor and a second resistor having an identical resistance, the series circuit electrically connected between a first terminal and a second terminal of the variable resistance circuit; a first field effect transistor (FET) having a source and a drain being electrically connected to emitters of the paired bipolar transistors, respectively; and a second FET having a drain, a gate being electrically connected to the drain thereof, the gate of the first FET, and a control terminal of variable resistance circuit, a source being electrically connected to a connection node between the first resistor and the second resistor, wherein the control current source adjusts the control current to allow transconductance of the second FET to be kept constant.

A charge amplifier circuit is provided. The charge amplifier circuit is couplable to a transducer that generates an electrical charge that varies with an external stimulus. The charge amplifier circuit includes an amplification stage having an input node, couplable to the transducer, and an output node. The amplification stage biases the input node at a first direct current (DC) voltage. The charge amplifier circuit includes a feedback circuit, which includes a feedback capacitor, electrically coupled between the input and output nodes of the amplification stage. The feedback circuit includes a resistor electrically coupled to the input node, and a level-shifter circuit, electrically coupled between the resistor and the output node. The level-shifter circuit biases the output node at a second DC voltage and as a function of a difference between the second DC voltage and a reference voltage.

A CMOS trans-impedance amplifier includes an inverting amplifier circuit and a feedback resistor. The inverting amplifier circuit includes an input end and an output end, and the feedback resistor is coupled therebetween. The inverting amplifier circuit includes at least three sequentially-connected amplifier units, and each amplifier unit includes at least three sequentially-connected nFETs, namely an input signal receiving part nFET, an intermediate part nFET and a DC signal receiving part nFET. A common connection terminal of the input signal receiving part nFET and the intermediate part nFET is configured to output an amplified voltage signal.

A CMOS trans-impedance amplifier includes an inverting amplifier circuit and a feedback resistor. The inverting amplifier circuit includes an input end and an output end, and the feedback resistor is coupled therebetween. The inverting amplifier circuit includes at least three sequentially-connected amplifier units, and each amplifier unit includes at least three sequentially-connected nFETs, namely an input signal receiving part nFET, an intermediate part nFET and a DC signal receiving part nFET. A common connection terminal of the input signal receiving part nFET and the intermediate part nFET is configured to output an amplified voltage signal.

A linear power supply circuit includes an output transistor provided between an input terminal to which an input voltage is applied and an output terminal to which an output voltage is applied, and a driver configured to drive the output transistor based on the difference between a voltage based on the output voltage and a reference voltage. The driver includes a differential amplifier, a converter, and a first capacitor provided between the output of the differential amplifier and a ground potential. The linear power supply circuit further includes a source follower circuit including a first transistor, and moreover includes a second transistor connected in series with the output transistor and constituting together with the first transistor a current mirror circuit, and a second capacitor connected to the control terminal of the first transistor.

An example current mirror arrangement includes a current mirror circuit, configured to receive an input current signal at an input transistor Q1 and output a mirrored signal at an output transistor Q2. The arrangement further includes a semi-cascoding circuit that includes transistors Q3, Q4, and a two-terminal passive network. The transistor Q3 is coupled to, and forms a cascode with, the output transistor Q2. The transistor Q4 is coupled to the transistor Q3. The base/gate of the transistor Q3 is coupled to a bias voltage Vref, and the base/gate of the transistor Q4 is coupled to a bias voltage Vref1 via the two-terminal passive network. Nonlinearity of the output current from such a current mirror arrangement may be reduced by selecting appropriate impedance of the two-terminal passive network and selecting appropriate bias voltages Vref and Vref1.

An example current mirror arrangement includes a current mirror circuit, configured to receive an input current signal at an input transistor Q1 and output a mirrored signal at an output transistor Q2. The arrangement further includes a semi-cascoding circuit that includes transistors Q3, Q4, and a two-terminal passive network. The transistor Q3 is coupled to, and forms a cascode with, the output transistor Q2. The transistor Q4 is coupled to the transistor Q3. The base/gate of the transistor Q3 is coupled to a bias voltage Vref, and the base/gate of the transistor Q4 is coupled to a bias voltage Vref1 via the two-terminal passive network. Nonlinearity of the output current from such a current mirror arrangement may be reduced by selecting appropriate impedance of the two-terminal passive network and selecting appropriate bias voltages Vref and Vref1.

The present invention relates generally to the field of electret capsule, and more particularly to a circuit configuration of an impedance converter integrated in an electret capsule such as for use in condenser microphones. The electret capsule of a microphone may include a gate biasing field effect transistor (FET) to facilitate biasing of a low noise FET. Advantageously, the use of low noise FET in the electret capsule of a microphone provides for a reduced cost, while achieving lower self-noise.

A high-speed buffer amplifier includes an input stage including a first channel coupled to receive differential inputs and a second channel coupled to receive the differential inputs; a middle stage including a first current source coupled to receive outputs of the second channel and electrically connected to power, a second current source coupled to receive outputs of the first channel and electrically connected to ground, and a floating current source electrically connected between the first current source and the second current source; and an output stage coupled to the middle stage to generate an output voltage. A shunt circuit is electrically connected between the first current source and the second current source, and configured to bypass the floating current source.