A signal process circuit includes a signal modulation unit, a first resistor, a second resistor, a first discharge unit, a second discharge unit and a discharge detection unit. The signal modulation unit is used to modulate an input signal for generating a modulated signal. The first resistor is coupled between the signal modulation unit and an operation node. The second resistor is coupled between the operation node and the signal modulation unit. The first discharge unit is coupled to the signal modulation unit. The discharge unit is coupled to the signal modulation unit. The discharge detection unit is coupled to the first discharge unit, the operation node and the second discharge unit for detecting an output common voltage and control a discharge path accordingly.

In a signal path comprising an analog path portion configured to operate in a plurality of output impedance modes including a high impedance mode with a first impedance and a low impedance mode with a second impedance, and a digital path portion having a variable digital gain and configured to convert a digital input signal and into an analog signal provided to the analog path portion, a method may include responsive to a condition for switching between the high impedance mode and the low impedance mode or vice versa, transitioning the output impedance continuously or in a series of steps between the first impedance and the second impedance or vice versa and, contemporaneously with transitioning the output impedance, transitioning the variable digital gain continuously or in a series of steps such to maintain a substantially constant overall path gain for the signal path remains substantially constant during transition.

In a signal path comprising an analog path portion configured to operate in a plurality of output impedance modes including a high impedance mode with a first impedance and a low impedance mode with a second impedance, and a digital path portion having a variable digital gain and configured to convert a digital input signal and into an analog signal provided to the analog path portion, a method may include responsive to a condition for switching between the high impedance mode and the low impedance mode or vice versa, transitioning the output impedance continuously or in a series of steps between the first impedance and the second impedance or vice versa and, contemporaneously with transitioning the output impedance, transitioning the variable digital gain continuously or in a series of steps such to maintain a substantially constant overall path gain for the signal path remains substantially constant during transition.

A buffer amplifier comprises a source follower and a feedback amplifier. The feedback amplifier may be configured to control a drain current of the source follower to remain substantially constant independent of a load.

According to an aspect, an audio amplifier includes a first sigma-delta modulator configured to receive a digital audio signal and generate a first multi-level output signal based on the audio signal, and a second sigma-delta modulator configured to receive the first multi-level output signal from the first sigma-delta modulator and generate a second multi-level output signal. The second multi-level output signal has a number of levels less than a number of levels of the first multi-level output signal.

According to an aspect, an audio amplifier includes a first sigma-delta modulator configured to receive a digital audio signal and generate a first multi-level output signal based on the audio signal, and a second sigma-delta modulator configured to receive the first multi-level output signal from the first sigma-delta modulator and generate a second multi-level output signal. The second multi-level output signal has a number of levels less than a number of levels of the first multi-level output signal.

A chopper amplifier circuit includes a first amplifier path with chopper circuitry, a switched-capacitor filter, and multiple gain stages. The chopper amplifier circuit also includes a second amplifier path with a feed-forward gain stage. A chopping frequency of the chopper circuitry is greater than a threshold frequency at which the second amplifier path is used instead of the first amplifier path.

Neuromodulation systems in accordance with embodiments of the invention can use a feed-forward common-mode cancellation (CMC) path to attenuate common-mode (CM) artifacts appearing at a voltage input, thus allowing for the simultaneous recording of neural data and stimulation of neurons. In several embodiments of the invention, the feed-forward CMC path is utilized to attenuate the common-mode swings at V.sub.in,CM, which can restore the linear operation of the front-end for differential signals. In several embodiments, the neuromodulation system may utilize an anti-alias filter (AAF) that includes a duty-cycles resistor (DCR) switching at a first frequency f.sub.1, followed by a DCR switching at a second frequency f.sub.2. The AAF allows for a significantly reduced second frequency f.sub.2 that enables the multi-rate DCR to increase the maximum realizable resistance, which is dependent upon the frequency ratio f.sub.1/f.sub.2.

A technique for receiving a DC or low frequency input signal using a chopper-stabilized amplifier includes chopping an input signal using a chopper clock signal to generate a chopped input signal. The input signal has a first voltage range and the chopper clock signal has a second voltage range. The chopper clock signal has peak-to-peak voltage over a period of the chopper clock signal. The peak-to-peak voltage is less than the first voltage range and is less than the second voltage range. A frequency of the input signal is at least an order of magnitude less than a frequency of the chopper clock signal. The second voltage range may be greater than or equal to the first voltage range. The technique may include generating a bias signal based on a voltage reference signal and an output signal having the first voltage range.

A technique for receiving a DC or low frequency input signal using a chopper-stabilized amplifier includes chopping an input signal using a chopper clock signal to generate a chopped input signal. The input signal has a first voltage range and the chopper clock signal has a second voltage range. The chopper clock signal has peak-to-peak voltage over a period of the chopper clock signal. The peak-to-peak voltage is less than the first voltage range and is less than the second voltage range. A frequency of the input signal is at least an order of magnitude less than a frequency of the chopper clock signal. The second voltage range may be greater than or equal to the first voltage range. The technique may include generating a bias signal based on a voltage reference signal and an output signal having the first voltage range.